28-GHz Bidirectional RF CMOS Amplifier Employing Body-Effect Control

This letter presents a 28-GHz bidirectional amplifier that operates as a low-noise amplifier (LNA) and a drive amplifier in the receiver (RX) (forward) and transmitter (TX) (backward) modes, respectively. In the proposed design, the bidirectional operation is realized through supply switching (SS) by utilizing the symmetric structure of a complementary metal–oxide–semiconductor (CMOS) device. Additionally, the body voltage control of an n-type MOS (nMOS) device is applied to attain symmetric and enhanced performance in both the forward and backward operations. The proposed design was fabricated using the 65-nm CMOS process and primarily characterized in the 28-GHz band. It achieves a nearly identical performance in both the forward and backward modes.

I. Introduction

Recently, the full-scale commercialization of the millimeter-wave (mmWave) fifth-generation (5G) new radio (NR) standard has been undertaken to offer a promising solution for handling the explosive growth of mobile data traffic [1]. To overcome the high path loss and signal-to-noise ratio degradation that occurs in the mmWave frequency band, a radio frequency (RF) transceiver must adopt a phased-array architecture with beam forming and beam steering capabilities [2], [3], [4]. However, realizing a low-cost and compact phased-array architecture is a critical concern, specifically in a mobile platform. Fig. 1(a) shows the block diagram of a conventional multielement phased-array RF front-end (FE) architecture, wherein several subblocks in individual transmitter (TX) and receiver (RX) paths are incorporated with TX/RX (T/R) switches (SWs). Owing to the stringent requirements of high output power and low noise performance, a gallium arsenide (GaAs)- or gallium nitride (GaN)-based power amplifier (PA) and low-noise amplifier (LNA) are normally used as the FE modules (FEMs) [5], [6], whereas the remaining subblocks, such as the variable gain amplifier (VGA), driving amplifier (DA), phase shifter (PS), divider/combiner, and mixers, are implemented using a cost-effective complementary metal–oxide–semiconductor (CMOS) technology. However, as the number of the element increases, system size and manufacturing cost rise accordingly. To secure high integration and cost reduction, various dual-/wideband [7], [8], [9], [10] and merged block [11], [12] circuit topologies have been demonstrated in the last decade. However, they still comprise separate RX and TX paths, which limit the increase in the number of elements. In contrast, as illustrated in Fig. 1(b), a bidirectional phased-array RF FE architecture is more beneficial in terms of chip size and cost because subblocks can be shared across both RX and TX modes [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24]. Moreover, this results in lower insertion loss through the elimination of the T/R SWs from the FEM. Fig. 1.

Block diagrams of (a) conventional and (b) bidirectional multielement phased-array RF FE architectures based on time-division duplexing operation.