Noise-Aware FET Circuit Design Based on C/ID-Invariant

This brief presents an analytical approach, supported by experimental data, to design analog circuits for given noise and speed specifications. As an extension to traditional design methodologies, i.e., Inversion Coefficient (IC) and $\mathrm { g_{m}/I_{D} }$ (GmID), the proposed approach aims to gain more in-depth insight, while providing appropriate analytical means for circuit design, at lower levels of computing complexity. Based on a recently proposed design approach, the $\mathrm { C/I_{D} }$ method relies on device characteristic capacitance, i.e., $\mathscr {C}_{S} = \mathrm { C_{S}/I_{D} }$ as an invariant, where $\mathrm {C_{S}}$ refers to the Field-Effect Transistor (FET) device self-loading capacitance. $\mathrm { C/I_{D} }$ provides the opportunity to derive closed-form solutions to some key design optimization problems such as power versus Gain Bandwidth (GBW) and noise trade-offs. Examples for common-source amplifiers and Ring Oscillators (RO) have been provided. A set of current-steering ROs has been designed and fabricated in $0.18~\mathrm {\mu }\text{m}$ technology based on the proposed flow. The circuit Phase Noise (PN) was characterized and compared to the predictions of the proposed design methodology, demonstrating favorable matching.

I. Introduction

Expansive industrial and academic driven interest exists regarding the systematic design, even automatic design, of Field-Effect Transistor (FET) based analog circuits. Such interest has produced an abundant wealth of literature in an effort to establish best practices of analog design. The most common design approaches rely on Inversion Coefficient (IC) and (GmID) methodologies [1], [2], [3]. The IC approach is based on existing compact models, such as [4], where normalized device saturation current, i.e., , being the device specific current, is selected as the main design variable [5]. Based on this, the circuit behavior in terms of desired specifications, such as Gain-Bandwidth product (GBW) and noise, are analyzed and used to deduce an optimal design point [6]. Despite an analytical nature, few iterations still might be required to finalize designs based on the IC methodology. Depending on target specifications, other normalized parameters such as , where refers to the self-loading capacitance of FET devices, and W being the effective channel width, can be used to enhance efficiency of the design flow [5], [7]. Whereas the GmID approach uses , which is the device transconductance efficiency for the main design parameter and is extracted with the remaining device parameters into Look-Up Tables (LUTs) [8], [2]. In tandem, search algorithms are employed to find optimal physical dimensions and biasing conditions that satisfy design constraints.