A Timing-Aware Configurable Adder Based on Timing Detection for Low-Voltage Computing

Low-voltage computing effectively saves energy in circuit operations, but it suffers from an increasing propagation delay. Approximate computing can significantly reduce the propagation delay by using a simplified or improved circuit, albeit with an inevitable accuracy loss. To address these challenges, a timing-aware configurable adder (TACA) is proposed to achieve a good trade-off between energy efficiency and accuracy at low operating voltages. This design relies on the functions of timing-error detection and correction (TEDC) for the newly-proposed accuracy-configurable full adders (ACFAs). The ACFA operates in an exact mode and two approximate modes by using four transistors as power gating. The TEDC generates timing-error signals when the delay violates the timing constraint due to voltage overscaling. Then, an improved configuration scheme is developed to enable the ACFA to work in an approximate mode by allowing for error signals at runtime. This approximation shortens the carry propagation chain. Thus, the TACA is adapted to timing conditions at different supply voltages by reducing the propagation delay rather than the operation frequency.

I. Introduction

Low-voltage operation provides an efficient way to reduce power in circuits and systems [1], [2], [3], [4]. However, due to process, voltage, and temperature (PVT) variations, it is challenging to satisfy all timing constraints [1]. The propagation delay of a circuit drastically increases as the supply voltage scales down, leading to considerable timing errors. Conventional designs avoid these errors by conservatively reserving timing margins and reducing the operation frequency. However, the use of these timing margins wastes excessive energy and reduces the throughput, because a circuit does not always work in the worst case. Applicable to the voltage overscaling (VOS) technique, configurable approximate computing (AC) emerges as a potential approach to overcoming these limitations [5], [6], [7].