pMOSFET with CVD-grown 2D semiconductor channel enabled by ultra-thin and fab-compatible spacer doping

We present the first demonstration of p-MOSFET with a high ON current of $10^{-5}\mathrm{A}/\mathrm{u}\mathrm{m}$ and good S.S. $\sim 80\mathrm{m}\mathrm{V}/\mathrm{d}\mathrm{e}\mathrm{c}$. MOSFETs have the advantage of lower access resistance compared to Schottky barrier FETs. This requires spacer doping. Here, we introduce a self-limiting, fab-compatible process which consists of $\mathrm{W}\mathrm{O}_{\mathrm{x}}$ obtained from $\mathrm{W}\mathrm{S}\mathrm{e}_{2}$ by O2 plasma conversion. We analyze the process condition which enhance the doping effect. We quantify the doping level and the impact of the channel bandgap. We demonstrate a self-aligned version of the spacer doping for MOSFET fabrication.

I. Introduction

2D materials have been proposed to replace the Si channel at contact gate pitch (CGP) less than 40nm because of expected superior electrostatic control in these very thin channels [1]. Transistor parasitic capacitance can also be reduced using thinner channels compared to Si in a nanosheet device architecture. To maintain low parasitic capacitance, sheet-to-sheet (StS) vertical separation(Fig. 1) needs to be kept at the lowest possible value. This value is limited by gate stack and doping height. For logic applications, minimizing capacitance has to be accompanied by the availability of n-and p-type transistors with high ON current. MOSFETs are known to have better transistor performance than Schottky barrier FET (as often used with the 2D channel) with the added challenge of requiring spacer doping [2]. Transistor resistance partitioning with a 2D channel reveals that 80% of consists of contact and spacer resistance (see Fig. 2). This is about twice as high as in Si. For details of the portiomng see [2]. Such high access resistance highlights the importance of introducing spacer doping and opting for MOSFET even for transistors with 2D channel.