Introduction
Next-generation high-performance computing and wireless networking packages, such as fan-out multichip module (FOMCM) packages, 2.5D silicon interposers, and fan-out embedded bridge (FOEB) packages, require considerably large body and die sizes and large pin counts to achieve a high speed, robust input/output functionality, and high reliability. Large FOMCM-FCBGA (flip chip ball grid array) packages require an underfill for the physical protection of the fragile silicon chip (or chip module) and copper pillar bump or solder bump and for the control of the warpage behavior of the package (Fig. 1).