Neutron Radiation Testing of RISC-V TMR Soft Processors on SRAM-Based FPGAs

Soft, configurable processors within field programmable gate array (FPGA) designs are susceptible to single-event upsets (SEUs). SEU mitigation techniques such as triple modular redundancy (TMR) and configuration memory scrubbing can be used to improve the reliability of soft processor designs. This article presents the improvements in the reliability of five different TMR soft processors within a neutron radiation environment. The TMR processors achieved up to a $75\times $ improvement in reliability at the cost of potentially $4.8\times $ resource utilization and an average 12.4% decrease in maximum frequency compared with the unmitigated designs. This work compares the metrics of reliability, power consumption, and performance among the default unmitigated processors and their TMR variations.

I. Introduction

Static random access memory (SRAM)-based field programmable gate arrays (FPGAs) often include soft processor implementations to provide software programmability. These soft processors are implemented using the FPGA’s reprogrammable resources such as lookup tables (LUTs), flip-flops (FFs), digital signal processing (DSP) units, and block RAM (BRAM). A variety of soft processor cores is available including open source RISC-V processor implementations using an open instruction set architecture (ISA). Integrating soft processors in an FPGA can be beneficial for applications in both terrestrial and space environments.