A Reusable UVM-SystemC Verification Environment for Simulation, Hardware Emulation, and FPGA Prototyping: Case Studies

Significant increase in design complexity has triggered the need for the reusability of verification environments across different platforms including digital simulators, hardware emulators, and FPGA prototyping systems. In this paper, we propose a reusable testbench verification environment using Universal Verification Methodology applied to SystemC language (UVM-SystemC) that can be deployed with Design-under-Tests (DUTs) between different simulators, hardware emulators, and FPGA prototyping systems without changing the source code. Two case studies, Advanced Encryption Standard (AES) core and, Network on Chip (NoC) mesh, are introduced and tested using proposed verification environments and industrial functional verification tools.