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David Black-Schaffer - IEEE Xplore Author Profile

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Author details

David Black-Schaffer

Publications

34

Citations

375

Publications by Year

20072023

Co-Authors:

Mehdi AlipourRicardo AlvesJames BalfourTrevor E. CarlsonGerman Ceballos

Show All Co-Authors (40)

David Black-Schaffer

Affiliation

Department of Information Technology

Uppsala University

Uppsala, Sweden

Publication Topics

Cache Misses,
Energy Conservation,
Access Latency,
Access Patterns,
Data Cache,
Energy Cost,
First-in-first-out,
Functional Unit,
L2 Cache,
Low Latency,
Per Cycle,
Percentage Points

Biography

David Black-Schaffer received the PhD degree in electrical engineering from Stanford University in 2008. He then worked on the design and implement of the OpenCL standard for heterogeneous computing at Apple, Inc., before joining Uppsala University, where he is currently an associate professor. His research interests include fast measurement, modeling, and simulation of shared resource contention, heterogeneous scheduling, and power-efficient memory systems. His research is funded by the Wallenberg Academy Fellowship program, the Swedish Science Council, the Swedish Foundation for Strategic Research's Future Research Leader program, the EU, and the Uppsala Programming for Multicore Architectures Research Center.(Based on document published on 28 March 2016).

Publications

34

Citations

375

Publications by Year

20072023

Co-Authors:

Mehdi Alipour
Ricardo Alves
James Balfour
Trevor E. Carlson
German Ceballos

Show All Co-Authors (40)

Author's Published Works

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Showing 1-25 of 34 results

Conferences (30)

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David Black-Schaffer(34)
Erik Hagersten(17)
Andreas Sembrant(9)
Stefanos Kaxiras(6)
Trevor E. Carlson(6)
Department of Information Technology, Uppsala University, Uppsala, Sweden(9)
Department of Information Technology, Uppsala University(5)
Uppsala University(4)
Department of Information Technology, Uppsala University, Sweden(3)
Computer Systems Laboratory, University of Stanford, Stanford, CA, USA(2)
IEEE Computer Architecture Letters(3)
2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)(2)
2017 IEEE International Symposium on Workload Characterization (IISWC)(2)
2007 Design, Automation & Test in Europe Conference & Exhibition(1)
2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT)(1)
IEEE(34)
Minneapolis, MN, USA(3)
San Diego, CA, USA(2)
Seattle, WA, USA(2)
Anchorage, AK, USA(1)
Atlanta, GA, USA(1)
Data Cache(16)
Cache Misses(14)
L2 Cache(14)
Benchmark(12)
Cache Size(12)

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Exploring the Latency Sensitivity of Cache Replacement Policies

Ahmed Nematallah;Chang Hyun Park;David Black-Schaffer

IEEE Computer Architecture Letters

Year: 2023 | Volume: 22, Issue: 2 | Journal Article |

Cited by: Papers (1)

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With DRAM latencies increasing relative to CPU speeds, the performance of caches has become more important. This has led to increasingly sophisticated replacement policies that require complex calculations to update their replacement metadata, which often require multiple cycles. To minimize the negative impact of these metadata updates, architects have focused on policies that incur as little upd...Show More

Exploring the Latency Sensitivity of Cache Replacement Policies

Ahmed Nematallah;Chang Hyun Park;David Black-Schaffer

IEEE Computer Architecture Letters

Year: 2023 | Volume: 22, Issue: 2 | Journal Article |

Architecturally-Independent and Time-Based Characterization of SPEC CPU 2017

Muhammad Hassan;Chang Hyun Park;David Black-Schaffer

2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

Year: 2020 | Conference Paper |

Cited by: Papers (3)

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Characterizing the memory behaviour of SPEC CPU benchmarks is critical to analyze bottlenecks in the execution. Unfortunately, most prior characterizations are tied to a particular system (e.g., via performance counters, fixed configurations) and missing important time-based behaviour (e.g., average over execution). While performance counters are accurate for that particular system, the results ar...Show More

Architecturally-Independent and Time-Based Characterization of SPEC CPU 2017

Muhammad Hassan;Chang Hyun Park;David Black-Schaffer

2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

Year: 2020 | Conference Paper |

Perforated Page: Supporting Fragmented Memory Allocation for Large Pages

Chang Hyun Park;Sanghoon Cha;Bokyeong Kim;Youngjin Kwon;David Black-Schaffer;Jaehyuk Huh

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)

Year: 2020 | Conference Paper |

Cited by: Papers (25)

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The availability of large pages has dramatically improved the efficiency of address translation for applications that use large contiguous regions of memory. However, large pages can be difficult to allocate due to fragmented memory, non-movable pages, or the need to split a large page into regular pages when part of the large page is forced to have a different permission status from the rest of t...Show More

Perforated Page: Supporting Fragmented Memory Allocation for Large Pages

Chang Hyun Park;Sanghoon Cha;Bokyeong Kim;Youngjin Kwon;David Black-Schaffer;Jaehyuk Huh

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)

Year: 2020 | Conference Paper |

Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors

Mehdi Alipour;Stefanos Kaxiras;David Black-Schaffer;Rakesh Kumar

2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)

Year: 2020 | Conference Paper |

Cited by: Papers (11)

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Flexible instruction scheduling is essential for performance in out-of-order processors. This is typically achieved by using CAM-based Instruction Queues (IQs) that provide complete flexibility in choosing ready instructions for execution, but at the cost of significant scheduling energy. In this work we seek to reduce the instruction scheduling energy by reducing the depth and width of the IQ. We...Show More

Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors

Mehdi Alipour;Stefanos Kaxiras;David Black-Schaffer;Rakesh Kumar

2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)

Year: 2020 | Conference Paper |

Filter Caching for Free: The Untapped Potential of the Store-Buffer

Ricardo Alves;Alberto Ros;David Black-Schaffer;Stefanos Kaxiras

2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA)

Year: 2019 | Conference Paper |

Cited by: Papers (3)

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Modern processors contain store-buffers to allow stores to retire under a miss, thus hiding store-miss latency. The store-buffer needs to be large (for performance) and searched on every load (for correctness), thereby making it a costly structure in both area and energy. Yet on every load, the store-buffer is probed in parallel with the L1 and TLB, with no concern for the store-buffer's intrinsic...Show More

Filter Caching for Free: The Untapped Potential of the Store-Buffer

Ricardo Alves;Alberto Ros;David Black-Schaffer;Stefanos Kaxiras

2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA)

Year: 2019 | Conference Paper |

FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors

Mehdi Alipour;Rakesh Kumar;Stefanos Kaxiras;David Black-Schaffer

2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Year: 2019 | Conference Paper |

Cited by: Papers (8)

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The number of instructions a processor's instruction queue can examine (depth) and the number it can issue together (width) determine its ability to take advantage of the ILP in an application. Unfortunately, increasing either the width or depth of the instruction queue is very costly due to the content-addressable logic needed to wakeup and select instructions out-of-order. This work makes the ob...Show More

FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors

Mehdi Alipour;Rakesh Kumar;Stefanos Kaxiras;David Black-Schaffer

2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Year: 2019 | Conference Paper |

Freeway: Maximizing MLP for Slice-Out-of-Order Execution

Rakesh Kumar;Mehdi Alipour;David Black-Schaffer

2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)

Year: 2019 | Conference Paper |

Cited by: Papers (18)

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Exploiting memory level parallelism (MLP) is crucial to hide long memory and last level cache access latencies. While out-of-order (OoO) cores, and techniques building on them, are effective at exploiting MLP, they deliver poor energy efficiency due to their complex hardware and the resulting energy overheads. As energy efficiency becomes the prime design constraint, we investigate low complexity/...Show More

Freeway: Maximizing MLP for Slice-Out-of-Order Execution

Rakesh Kumar;Mehdi Alipour;David Black-Schaffer

2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)

Year: 2019 | Conference Paper |

Tail-PASS: Resource-Based Cache Management for Tiled Graphics Rendering Hardware

Germán Ceballos;Erik Hagersten;David Black-Schaffer

2018 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Ubiquitous Computing & Communications, Big Data & Cloud Computing, Social Computing & Networking, Sustainable Computing & Communications (ISPA/IUCC/BDCloud/SocialCom/SustainCom)

Year: 2018 | Conference Paper |

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Modern graphics rendering is a very expensive process and can account for 60% of the battery consumption on current games. Much of the cost comes from the high memory bandwidth of rendering complex graphics. To render a frame, multiple smaller rendering passes called scenes are executed, with each one tiled for parallel execution. The data for each scene comes from hundreds of software resources (...Show More

Tail-PASS: Resource-Based Cache Management for Tiled Graphics Rendering Hardware

Germán Ceballos;Erik Hagersten;David Black-Schaffer

2018 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Ubiquitous Computing & Communications, Big Data & Cloud Computing, Social Computing & Networking, Sustainable Computing & Communications (ISPA/IUCC/BDCloud/SocialCom/SustainCom)

Year: 2018 | Conference Paper |

Dynamically Disabling Way-prediction to Reduce Instruction Replay

Ricardo Alves;Stefanos Kaxiras;David Black-Schaffer

2018 IEEE 36th International Conference on Computer Design (ICCD)

Year: 2018 | Conference Paper |

Cited by: Papers (6)

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Way-predictors have long been used to reduce dynamic cache energy without the performance loss of serial caches. However, they produce variable-latency hits, as incorrect predictions increase load-to-use latency. While the performance impact of these extra cycles has been well-studied, the need to replay subsequent instructions in the pipeline due to the load latency increase has been ignored. In ...Show More

Dynamically Disabling Way-prediction to Reduce Instruction Replay

Ricardo Alves;Stefanos Kaxiras;David Black-Schaffer

2018 IEEE 36th International Conference on Computer Design (ICCD)

Year: 2018 | Conference Paper |

Behind the Scenes: Memory Analysis of Graphical Workloads on Tile-Based GPUs

German Ceballos;Andreas Sembrant;Trevor E. Carlson;David Black-Schaffer

2018 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

Year: 2018 | Conference Paper |

Cited by: Papers (5)

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Graphics rendering is a complex multi-step process whose data demands typically dominate memory system design in SoCs. GPUs create images by merging many simpler scenes for each frame. For performance, scenes are tiled into parallel tasks which produce different parts of the final output. This execution model results in complex memory behavior with bandwidth demands and data sharing varying over t...Show More

Behind the Scenes: Memory Analysis of Graphical Workloads on Tile-Based GPUs

German Ceballos;Andreas Sembrant;Trevor E. Carlson;David Black-Schaffer

2018 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

Year: 2018 | Conference Paper |

Analyzing graphics workloads on tile-based GPUs

Germán Ceballos;Andreas Sembrant;Trevor E. Carlson;David Black-Schaffer

2017 IEEE International Symposium on Workload Characterization (IISWC)

Year: 2017 | Conference Paper |

Cited by: Papers (1)

HTML

Graphics rendering is a complex, multi-step process whose data demands typically dominate memory system design in SoCs. GPUs create images by merging many, simpler scenes for each frame. For performance, scenes are tiled into parallel tasks, each of which produces different parts of the final output. This execution model results in complex memory behavior, whose bandwidth demands, reuse and sharin...Show More

Analyzing graphics workloads on tile-based GPUs

Germán Ceballos;Andreas Sembrant;Trevor E. Carlson;David Black-Schaffer

2017 IEEE International Symposium on Workload Characterization (IISWC)

Year: 2017 | Conference Paper |

A graphics tracing framework for exploring CPU+GPU memory systems

Andreas Sembrant;Trevor E. Carlson;Erik Hagersten;David Black-Schaffer

2017 IEEE International Symposium on Workload Characterization (IISWC)

Year: 2017 | Conference Paper |

Cited by: Papers (10) | Patents (2)

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Modern SoCs contain CPU and GPU cores to execute both general purpose and highly-parallel graphics workloads. While the primary use of the GPU is for rendering graphics, the effects of graphics workloads on the overall system have received little attention. The primary reason for this is the lack of efficient tools and simulators for modern graphics applications. In this work, we present GLTraceSi...Show More

A graphics tracing framework for exploring CPU+GPU memory systems

Andreas Sembrant;Trevor E. Carlson;Erik Hagersten;David Black-Schaffer

2017 IEEE International Symposium on Workload Characterization (IISWC)

Year: 2017 | Conference Paper |

Addressing Energy Challenges in Filter Caches

Ricardo Alves;Nikos Nikoleris;Stefanos Kaxiras;David Black-Schaffer

2017 29th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

Year: 2017 | Conference Paper |

Cited by: Papers (4)

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Filter caches and way-predictors are common approaches to improve the efficiency and/or performance of first-level caches. Filter caches use a small L0 to provide more efficient and faster access to a small subset of the data, and work well for programs with high locality. Way-predictors improve efficiency by accessing only the way predicted, which alleviates the need to read all ways in parallel ...Show More

Addressing Energy Challenges in Filter Caches

Ricardo Alves;Nikos Nikoleris;Stefanos Kaxiras;David Black-Schaffer

2017 29th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

Year: 2017 | Conference Paper |

POSTER: Putting the G back into GPU/CPU Systems Research

Andreas Sembrant;Trevor E. Carlson;Erik Hagersten;David Black-Schaffer

2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT)

Year: 2017 | Conference Paper |

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Modern SoCs contain several CPU cores and many GPU cores to execute both general purpose and highly-parallel graphics workloads. In many SoCs, more area is dedicated to graphics than to general purpose compute. Despite this, the micro-architecture research community primarily focuses on GPGPU and CPU-only research, and not on graphics (the primary workload for many SoCs). The main reason for this ...Show More

POSTER: Putting the G back into GPU/CPU Systems Research

Andreas Sembrant;Trevor E. Carlson;Erik Hagersten;David Black-Schaffer

2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT)

Year: 2017 | Conference Paper |

A Split Cache Hierarchy for Enabling Data-Oriented Optimizations

Andreas Sembrant;Erik Hagersten;David Black-Schaffer

2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)

Year: 2017 | Conference Paper |

Cited by: Papers (7)

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Today's caches tightly couple data with metadata (Address Tags) at the cache line granularity. The co-location of data and its identifying metadata means that they require multiple approaches to locate data (associative way searches and level-by-level searches), evict data (coherent writebacks buffers and associative level-by-level searches) and keep data coherent (directory indirections and assoc...Show More

A Split Cache Hierarchy for Enabling Data-Oriented Optimizations

Andreas Sembrant;Erik Hagersten;David Black-Schaffer

2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)

Year: 2017 | Conference Paper |

Partitioning GPUs for Improved Scalability

Johan Janzén;David Black-Schaffer;Andra Hugo

2016 28th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

Year: 2016 | Conference Paper |

Cited by: Papers (7) | Patents (1)

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To port applications to GPUs, developers need to express computational tasks as highly parallel executions with tens of thousands of threads to fill the GPU's compute resources. However, while this will fill the GPU's resources, it does not necessarily deliver the best efficiency, as the task may scale poorly when run with sufficient parallelism to fill the GPU. In this work we investigate how we ...Show More

Partitioning GPUs for Improved Scalability

Johan Janzén;David Black-Schaffer;Andra Hugo

2016 28th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

Year: 2016 | Conference Paper |

Data placement across the cache hierarchy: Minimizing data movement with reuse-aware placement

Andreas Sembrant;Erik Hagersten;David Black-Schaffer

2016 IEEE 34th International Conference on Computer Design (ICCD)

Year: 2016 | Conference Paper |

Cited by: Papers (4)

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Modern processors employ multiple levels of caching to address bandwidth, latency and performance requirements. The behavior of these hierarchies is determined by their approach to data placement and data eviction. Recent research has developed many intelligent data eviction policies, but cache hierarchies remain primarily either exclusive or inclusive with regards to data placement. This means th...Show More

Data placement across the cache hierarchy: Minimizing data movement with reuse-aware placement

Andreas Sembrant;Erik Hagersten;David Black-Schaffer

2016 IEEE 34th International Conference on Computer Design (ICCD)

Year: 2016 | Conference Paper |

Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics

Sam Van den Steen;Stijn Eyerman;Sander De Pestel;Moncef Mechri;Trevor E. Carlson;David Black-Schaffer;Erik Hagersten;Lieven Eeckhout

IEEE Transactions on Computers

Year: 2016 | Volume: 65, Issue: 12 | Journal Article |

Cited by: Papers (29)

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Optimizing processors for (a) specific application(s) can substantially improve energy-efficiency. With the end of Dennard scaling, and the corresponding reduction in energy-efficiency gains from technology scaling, such approaches may become increasingly important. However, designing application-specific processors requires fast design space exploration tools to optimize for the targeted applicat...Show More

Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics

Sam Van den Steen;Stijn Eyerman;Sander De Pestel;Moncef Mechri;Trevor E. Carlson;David Black-Schaffer;Erik Hagersten;Lieven Eeckhout

IEEE Transactions on Computers

Year: 2016 | Volume: 65, Issue: 12 | Journal Article |

AREP: Adaptive Resource Efficient Prefetching for Maximizing Multicore Performance

Muneeb Khan;Michael A. Laurenzanoy;Jason Marsy;Erik Hagersten;David Black-Schaffer

2015 International Conference on Parallel Architecture and Compilation (PACT)

Year: 2015 | Conference Paper |

Cited by: Papers (14)

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Modern processors widely use hardware prefetching to hide memory latency. While aggressive hardware prefetchers can improve performance significantly for some applications, they can limit the overall performance in highly-utilized multicore processors by saturating the offchip bandwidth and wasting last-level cache capacity. Co-executing applications can slowdown due to contention over these share...Show More

AREP: Adaptive Resource Efficient Prefetching for Maximizing Multicore Performance

Muneeb Khan;Michael A. Laurenzanoy;Jason Marsy;Erik Hagersten;David Black-Schaffer

2015 International Conference on Parallel Architecture and Compilation (PACT)

Year: 2015 | Conference Paper |

Full Speed Ahead: Detailed Architectural Simulation at Near-Native Speed

Andreas Sandberg;Nikos Nikoleris;Trevor E. Carlson;Erik Hagersten;Stefanos Kaxiras;David Black-Schaffer

2015 IEEE International Symposium on Workload Characterization

Year: 2015 | Conference Paper |

Cited by: Papers (34)

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Cycle-level micro architectural simulation is the de-facto standard to estimate performance of next-generation platforms. Unfortunately, the level of detail needed for accurate simulation requires complex, and therefore slow, simulation models that run at speeds that are thousands of times slower than native execution. With the introduction of sampled simulation, it has become possible to simulate...Show More

Full Speed Ahead: Detailed Architectural Simulation at Near-Native Speed

Andreas Sandberg;Nikos Nikoleris;Trevor E. Carlson;Erik Hagersten;Stefanos Kaxiras;David Black-Schaffer

2015 IEEE International Symposium on Workload Characterization

Year: 2015 | Conference Paper |

Micro-architecture independent analytical processor performance and power modeling

Sam Van den Steen;Sander De Pestel;Moncef Mechri;Stijn Eyerman;Trevor Carlson;David Black-Schaffer;Erik Hagersten;Lieven Eeckhout

2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

Year: 2015 | Conference Paper |

Cited by: Papers (25)

HTML

Optimizing processors for specific application(s) can substantially improve energy-efficiency. With the end of Dennard scaling, and the corresponding reduction in energyefficiency gains from technology scaling, such approaches may become increasingly important. However, designing applicationspecific processors require fast design space exploration tools to optimize for the targeted application(s)....Show More

Micro-architecture independent analytical processor performance and power modeling

Sam Van den Steen;Sander De Pestel;Moncef Mechri;Stijn Eyerman;Trevor Carlson;David Black-Schaffer;Erik Hagersten;Lieven Eeckhout

2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

Year: 2015 | Conference Paper |

Navigating the cache hierarchy with a single lookup

Andreas Sembrant;Erik Hagersten;David Black-Schaffer

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

Year: 2014 | Conference Paper |

Cited by: Papers (3) | Patents (1)

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Modern processors optimize for cache energy and performance by employing multiple levels of caching that address bandwidth, low-latency and high-capacity. A request typically traverses the cache hierarchy, level by level, until the data is found, thereby wasting time and energy in each level. In this paper, we present the Direct-to-Data (D2D) cache that locates data across the entire cache hierarc...Show More

Navigating the cache hierarchy with a single lookup

Andreas Sembrant;Erik Hagersten;David Black-Schaffer

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

Year: 2014 | Conference Paper |

Modeling performance variation due to cache sharing

Andreas Sandberg;Andreas Sembrant;Erik Hagersten;David Black-Schaffer

2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)

Year: 2013 | Conference Paper |

Cited by: Papers (31)

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Shared cache contention can cause significant variability in the performance of co-running applications from run to run. This variability arises from different overlappings of the applications' phases, which can be the result of offsets in application start times or other delays in the system. Understanding this variability is important for generating an accurate view of the expected impact of cac...Show More

Modeling performance variation due to cache sharing

Andreas Sandberg;Andreas Sembrant;Erik Hagersten;David Black-Schaffer

2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)

Year: 2013 | Conference Paper |

Efficient techniques for predicting cache sharing and throughput

Andreas Sandberg;David Black-Schaffer;Erik Hagersten

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)

Year: 2012 | Conference Paper |

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This work addresses the modeling of shared cache contention in multicore systems and its impact on throughput and bandwidth. We develop two simple and fast cache sharing models for accurately predicting shared cache allocations for random and LRU caches.Show More

Efficient techniques for predicting cache sharing and throughput

Andreas Sandberg;David Black-Schaffer;Erik Hagersten

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)

Year: 2012 | Conference Paper |

Bandwidth Bandit: Quantitative characterization of memory contention

David Eklov;Nikos Nikoleris;David Black-Schaffer;Erik Hagersten

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)

Year: 2012 | Conference Paper |

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Applications that are co-scheduled on a multi-core compete for shared resources, such as cache capacity and memory bandwidth. The performance degradation resulting from this contention can be substantial, which makes it important to effectively manage these shared resources. This, however, requires quantitative insight into how applications are impacted by such contention. In this paper we present...Show More

Bandwidth Bandit: Quantitative characterization of memory contention

David Eklov;Nikos Nikoleris;David Black-Schaffer;Erik Hagersten

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)

Year: 2012 | Conference Paper |

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