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Kyung-Hoon Lee - IEEE Xplore Author Profile

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Kyung-Hoon Lee

Also published under: Kyung-hoon Lee

Publications
6
Citations
51
Publications by Year
20062011
Co-Authors:
Show All Co-Authors (22)
Image of author Kyung-Hoon Lee

Kyung-Hoon Lee

Also published under: Kyung-hoon Lee

Affiliation

Department of Electronic Engineering
Sogang University
Seoul, South Korea

Publication Topics

Biography

Kyung-Hoon Lee received the B.S., M.S., and Ph.D. degrees in electronics engineering from Sogang University, Seoul, Korea, in 2004, 2006, and 2011, respectively.,He is currently a Senior Engineer at Samsung Electronics, Korea. His current interests are in the design of high-resolution low-power CMOS data converters and very high-speed mixed-mode integrated systems.(Based on document published on 17 March 2011).
Publications
6
Citations
51
Publications by Year
20062011
Co-Authors:
Show All Co-Authors (22)
Author's Published Works

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A 12b 50 MS/s 21.6 mW 0.18 \mum CMOS ADC Maximally Sharing Capacitors and Op-Amps

Kyung-Hoon Lee;Kwang-Soo Kim;Seung-Hoon Lee

IEEE Transactions on Circuits and Systems I: Regular Papers
Year: 2011 | Volume: 58, Issue: 9 | Journal Article |
Cited by: Papers (31)
A 12b 50 MS/s 0.18 μ m CMOS pipeline ADC is described. The proposed capacitor and operational amplifier (op-amp) sharing techniques merge the front-end sample-and-hold amplifier (SHA) and the first multiplying digital-to-analog converter (MDAC1) to achieve low power without an additional reset timing and a memory effect. The second and third MDACs share a single op-amp to reduce power consumption ...Show More

A 12b 50 MS/s 21.6 mW 0.18 $\mu$m CMOS ADC Maximally Sharing Capacitors and Op-Amps

Kyung-Hoon Lee;Kwang-Soo Kim;Seung-Hoon Lee

Year: 2011 | Volume: 58, Issue: 9 | Journal Article |

A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers

Young-Ju Kim;Hee-Cheol Choi;Kyung-Hoon Lee;Gil-Cho Ahn;Seung-Hoon Lee;Ju-Hwa Kim;Kyoung-Jun Moon;Michael Choi;Kyoung-Ho Moon;Ho-Jin Park;Byeong-Ha Park

2009 IEEE Custom Integrated Circuits Conference
Year: 2009 | Conference Paper |
Cited by: Papers (13)
A 12-bit 1.2V 160MS/s pipeline ADC for high-definition video systems is presented. The proposed multipath frequency-compensation technique enables the conventional RNMC-based three-stage amplifier to achieve a stable operation at a sampling rate of 160MS/s. The measured differential and integral nonlinearities of the prototype ADC implemented in a 65nm CMOS process are less than 0.69LSB and 1.00LS...Show More

A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers

Young-Ju Kim;Hee-Cheol Choi;Kyung-Hoon Lee;Gil-Cho Ahn;Seung-Hoon Lee;Ju-Hwa Kim;Kyoung-Jun Moon;Michael Choi;Kyoung-Ho Moon;Ho-Jin Park;Byeong-Ha Park

Year: 2009 | Conference Paper |

A 14b 100MS/s 3.4mm2 145mW 0.18um CMOS Pipeline A/D Converter

Kyung-Hoon Lee;Young-Jae Cho;Hee-Cheol Choi;Yong-Hyun Park;Doo-Hwan Sa;Young-Lok Kim;Seung-Hoon Lee

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Year: 2006 | Conference Paper |
This work proposes a 14b 100MS/s 0.18mum CMOS ADC for the fourth-generation mobile communication systems. The proposed 3-stage pipeline ADC, whose architecture is verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b...Show More

A 14b 100MS/s 3.4mm2 145mW 0.18um CMOS Pipeline A/D Converter

Kyung-Hoon Lee;Young-Jae Cho;Hee-Cheol Choi;Yong-Hyun Park;Doo-Hwan Sa;Young-Lok Kim;Seung-Hoon Lee

Year: 2006 | Conference Paper |

A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems

Young-Jae Cho;Kyung-Hoon Lee;Hee-Cheol Choi;Young-Ju Kim;Kyoung-Jun Moon;Seung-Hoon Lee;Seok-Bong Hyun;Seong-Su Park

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Year: 2006 | Conference Paper |
Cited by: Papers (1)
This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference preamplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble code correction circuits to opt...Show More

A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems

Young-Jae Cho;Kyung-Hoon Lee;Hee-Cheol Choi;Young-Ju Kim;Kyoung-Jun Moon;Seung-Hoon Lee;Seok-Bong Hyun;Seong-Su Park

Year: 2006 | Conference Paper |

A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications

Young-jae Cho;Doo-hwan Sa;Yong-woo Kim;Kyung-hoon Lee;Hee-cheol Choi;Seung-hoon Lee;Young-deuk Jeon;Seung-chul Lee;Jong-kee Kwon

IEEE Custom Integrated Circuits Conference 2006
Year: 2006 | Conference Paper |
Cited by: Papers (2) | Patents (1)
A 10b two-stage pipeline ADC implemented in a 0.13mum CMOS operates at dual sampling clock rates of 25MS/s and 10MS/s based on a switched-bias power-reduction technique for low-power system applications. The prototype ADC shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling rates up to 25MS/s. The ADC occupies an active die area of 0.8mm2 and consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s,...Show More

A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications

Young-jae Cho;Doo-hwan Sa;Yong-woo Kim;Kyung-hoon Lee;Hee-cheol Choi;Seung-hoon Lee;Young-deuk Jeon;Seung-chul Lee;Jong-kee Kwon

Year: 2006 | Conference Paper |

A Calibration-Free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS Pipeline ADC with High-Matching 3-D Symmetric Capacitors

Young-jae Cho;Kyung-hoon Lee;Hee-cheol Choi;Seung-hoon Lee;Kyoung-ho Moon;Jae-whui Kim

IEEE Custom Integrated Circuits Conference 2006
Year: 2006 | Conference Paper |
Cited by: Papers (4)
A 14b 70MS/s 3-stage pipeline ADC in a 0.13mum CMOS process employs signal insensitive 3D fully symmetric capacitors for high matching accuracy without any calibration scheme. The prototype ADC with a 0.35mum minimum channel length for 2.5V system applications shows measured differential and integral nonlinearities of 0.65LSB and 1.80LSB at 14b, occupies a die area of 3.3mm2, and consumes 235mW at...Show More

A Calibration-Free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS Pipeline ADC with High-Matching 3-D Symmetric Capacitors

Young-jae Cho;Kyung-hoon Lee;Hee-cheol Choi;Seung-hoon Lee;Kyoung-ho Moon;Jae-whui Kim

Year: 2006 | Conference Paper |

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