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Tadeusz Tomczak - IEEE Xplore Author Profile
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Tadeusz Tomczak

Publications
4
Citations
56
Publications by Year
20062018
Co-Authors:
Image of author Tadeusz Tomczak

Tadeusz Tomczak

Affiliation

Faculty of Electronics
Computer Engineering at Wroclaw University of Science and Technology
Wroclaw, Poland

Publication Topics

Biography

Tadeusz Tomczak received MS and PhD degrees in computer science all from the Institute of Computers, Control, and Robotics, Wroclaw University of Technology, Poland, in 2002 and 2007 respectively. His research interests include residue number systems, fast computational hardware and parallel computing.(Based on document published on 27 February 2018).
Publications
4
Citations
56
Publications by Year
20062018
Co-Authors:
Author's Published Works

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Sparse Geometries Handling in Lattice Boltzmann Method Implementation for Graphic Processors

Tadeusz Tomczak;Roman G. Szafran

IEEE Transactions on Parallel and Distributed Systems
Year: 2018 | Volume: 29, Issue: 8 | Journal Article |
Cited by: Papers (11)
We describe a high-performance implementation of the lattice Boltzmann method (LBM) for sparse geometries on graphic processors. In our implementation we cover the whole geometry with a uniform mesh of small tiles and carry out calculations for each tile independently with proper data synchronization at the tile edges. For this method, we provide both a theoretical analysis of complexity and the r...Show More

Sparse Geometries Handling in Lattice Boltzmann Method Implementation for Graphic Processors

Tadeusz Tomczak;Roman G. Szafran

Year: 2018 | Volume: 29, Issue: 8 | Journal Article |

Fast Sign Detection for RNS (2^{n}-1,2^{n},2^{n}+1)

Tadeusz Tomczak

IEEE Transactions on Circuits and Systems I: Regular Papers
Year: 2008 | Volume: 55, Issue: 6 | Journal Article |
Cited by: Papers (33)
In this paper, we propose a fast algorithm for sign-extraction of a number given in the Residue Number System (2n-1,2n,2n+1) . The algorithm can be implemented using three n-bit wide additions, two of which can be done in parallel. It can be used in a wide variety of problems, i.e., in algorithms for dividing numbers in the RNS, or in evaluating the sign of determinant in computational geometry, e...Show More

Fast Sign Detection for RNS (2^{n}-1,2^{n},2^{n}+1)

Tadeusz Tomczak

Year: 2008 | Volume: 55, Issue: 6 | Journal Article |

Residue Arithmetic in FPGA Matrices

Tadeusz Tomczak

2006 International Conference on Dependability of Computer Systems
Year: 2006 | Conference Paper |
Cited by: Papers (4) | Patents (1)
In this work, presented is the methodology of designing residue generators and arithmetic units for modern FPGA matrices. The proposed algorithms take advantage of dedicated logic for high-speed arithmetic present in Xilinx Spartan-2 and Virtex FPGA families. Comparing to implementations published so far, which are based mainly on look_up table solutions, new method results in better area-time eff...Show More

Residue Arithmetic in FPGA Matrices

Tadeusz Tomczak

Year: 2006 | Conference Paper |

Low-cost and Universal Secure Scan: a Design- Architecture for Crypto Chips

Marcin Gomulkiewicz;Maciej Nikodem;Tadeusz Tomczak

2006 International Conference on Dependability of Computer Systems
Year: 2006 | Conference Paper |
Cited by: Papers (8) | Patents (1)
Scan based design-for-test is a powerful testing scheme, but it can be used to retrieve secrets stored inside a crypto device. In this paper, we propose a novel scan based DFT architecture called secure scan that maintains the high test quality without compromising the security. Moreover our proposition is universal and can be easily implemented as an extension of the standard scan chain architect...Show More

Low-cost and Universal Secure Scan: a Design- Architecture for Crypto Chips

Marcin Gomulkiewicz;Maciej Nikodem;Tadeusz Tomczak

Year: 2006 | Conference Paper |

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