Mototsugu Okushima - IEEE Xplore Author Profile
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Mototsugu Okushima

Also published under: M. Okushima

Publications
15
Citations
62
Publications by Year
20062024
Co-Authors:
Show All Co-Authors (23)
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Mototsugu Okushima

Also published under: M. Okushima

Affiliation

Renesas Electronics Corporation, Tokyo, Japan

Publication Topics

Biography

Mototsugu Okushima received the M.E. degree in electrical engineering from Osaka University, Japan, in 1997. He joined NEC Corporation, as an Engineer of the development of advanced CMOS devices. In 2000, he was assigned to the development for ESD protection circuits. From 2007 to 2008, he was with IMEC, Belgium, to study ESD protection for RF circuits. He currently enjoys the challenges of providing ESD solutions to products of cutting edge CMOS, flash embedded MCU, and high voltage analog BCD, as a Senior ESD Manager with Renesas. He is serving as a TPC Member of EOSESD Symposium, IRPS, International ESD workshop, and ESREF.(Based on document published on 11 November 2020).
Publications
15
Citations
62
Publications by Year
20062024
Co-Authors:
Show All Co-Authors (23)
Author's Published Works

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On-Chip ESD Current Sensor for Nanosecond Oscillation Waveform Over Ampere Detecting

Kazuki Shimada;Mototsugu Okushima

2024 14th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)
Year: 2024 | Conference Paper |
To analyze IC destruction and malfunction due to ESD (IEC61000-4-2), we proposed an on-chip current sensor that can accurately capture the entire ESD current waveform flowing into the IC that oscillates significantly for positive and negative in the nanosecond range. Measurement accuracy has improved by compensating for measurement errors caused by voltage overshoot in the nanosecond range of the ...Show More

On-Chip ESD Current Sensor for Nanosecond Oscillation Waveform Over Ampere Detecting

Kazuki Shimada;Mototsugu Okushima

Year: 2024 | Conference Paper |

On-chip ESD Current Sensor for System-level ESD Detection in High Voltage BiCD Technology

Kazuki Shimada;Mototsugu Okushima

2022 44th Annual EOS/ESD Symposium (EOS/ESD)
Year: 2022 | Conference Paper |
Cited by: Papers (3)
On-chip ESD current sensor to capture 1st /2nd peak current waveform of system-level ESD injected into IC in high voltage BiCD technology is proposed. Measurement error due to voltage overshoot of high voltage ESD diode is corrected. The sensor would be a key component for avoiding IC destruction or malfunction by system-level ESD.Show More

On-chip ESD Current Sensor for System-level ESD Detection in High Voltage BiCD Technology

Kazuki Shimada;Mototsugu Okushima

Year: 2022 | Conference Paper |

Low-Leakage and Variable VHOLD Power Clamp for Wide Stress Time Range From ESD to Surge Test

Koki Narita;Mototsugu Okushima

IEEE Transactions on Device and Materials Reliability
Year: 2020 | Volume: 20, Issue: 4 | Journal Article |
Cited by: Papers (4)
In recent years, on-chip clamp designs for enhancing destructive immunity of ICs mounted on systems against residual currents of system level immunity tests have been proposed. To cope with a long duration pulse (several tens μs) such as a surge immunity test is one of the issues of the system level on-chip clamp. A clamp combined RC-trigger and static trigger is one approach to achieve both a low...Show More

Low-Leakage and Variable VHOLD Power Clamp for Wide Stress Time Range From ESD to Surge Test

Koki Narita;Mototsugu Okushima

Year: 2020 | Volume: 20, Issue: 4 | Journal Article |

A Study of On-state Breakdown Decreasing of nLDMOSFETs by Hole Current Increase Depending on Drain Pulse Rise Time

Takahiro Mori;Tomonari Yamaguchi;Takeshi Kamino;Junji Tsuruta;Mototsugu Okushima;Hirokazu Sayama;Koji Iizuka

2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD)
Year: 2020 | Conference Paper |
The introduction of a p-type RESURF (REduced SURface Field) layer under an n-type drift region is a well-known means to improve the specific on-resistance (R$_{\mathbf{sp}}$) versus the off-state breakdown voltage (BV$_{\mathbf{off}}$) trade-off and reduce hot carrier injection (HCI) degradation in n-channel LDMOSFETs (nLDMOSFETs). The p-type RESURF layer also works as a punch-through stopper to m...Show More

A Study of On-state Breakdown Decreasing of nLDMOSFETs by Hole Current Increase Depending on Drain Pulse Rise Time

Takahiro Mori;Tomonari Yamaguchi;Takeshi Kamino;Junji Tsuruta;Mototsugu Okushima;Hirokazu Sayama;Koji Iizuka

Year: 2020 | Conference Paper |

A Variable VH Combined Power Clamp for System Level ESD/Surge Immunity Enhancement with Low Leakage

Koki Narita;Mototsugu Okushima

2019 41st Annual EOS/ESD Symposium (EOS/ESD)
Year: 2019 | Conference Paper |
Cited by: Papers (6)
An on-chip power clamp which combined RC and static trigger circuits for the system level ESD/EFT/Surge enhancement is proposed. The proposed clamp can achieve the higher immunity against longer pulses such as the surge event compared to the conventional combined clamp without increasing the leakage current of the trigger circuit using a variable holding voltage technique.Show More

A Variable VH Combined Power Clamp for System Level ESD/Surge Immunity Enhancement with Low Leakage

Koki Narita;Mototsugu Okushima

Year: 2019 | Conference Paper |

Low Clamping Voltage Protection for Improvements of Powered ESD Robustness

Koki Narita;Mototsugu Okushima

2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)
Year: 2018 | Conference Paper |
Cited by: Papers (9)
An on-chip protection for improvements of powered ESD robustness is presented. The proposed power clamp achieved to reduce the clamping voltage against powered ESD events compared to a conventional RC-riggered clamp by extending of the big-MOS active time with also consideration to false activation.Show More

Low Clamping Voltage Protection for Improvements of Powered ESD Robustness

Koki Narita;Mototsugu Okushima

Year: 2018 | Conference Paper |

CDM protection design using internal power node for cross power domain in 16nm CMOS technology

Koki Narita;Mototsugu Okushima

2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)
Year: 2016 | Conference Paper |
Cited by: Papers (5)
This paper presents a CDM protection design for cross-domain interface circuits using an internal cross clamp as voltage divider between the internal power supply node of analog circuits and the digital GND node. The proposed protection circuit meets high CDM current request from large packaged IC with 16nm FinFET.Show More

CDM protection design using internal power node for cross power domain in 16nm CMOS technology

Koki Narita;Mototsugu Okushima

Year: 2016 | Conference Paper |

CDM secondary clamp of RX and TX for high speed SerDes application in 40nm CMOS technology

Mototsugu Okushima;Junji Tsuruta

EOS/ESD Symposium Proceedings
Year: 2011 | Conference Paper |
Cited by: Papers (1)
Novel secondary clamp solutions to boost CDM robustness for both RX and TX circuits along with dual diode of 135fF to meet over 6-G bit/s SerDes are presented. For RX circuit, active PMOS clamp with no voltage overshoot is used as secondary clamp to GND. For TX circuit, by constructing a secondary ESD path through the pre-driver and pumping-up the gate node of the main-driver, an additional series...Show More

CDM secondary clamp of RX and TX for high speed SerDes application in 40nm CMOS technology

Mototsugu Okushima;Junji Tsuruta

Year: 2011 | Conference Paper |

Cross domain protection analysis and verification using whole chip ESD simulation

Mototsugu Okushima;Tomohiro Kitayama;Susumu Kobayashi;Tetsuya Kato;Morihisa Hirata

Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010
Year: 2010 | Conference Paper |
Cited by: Papers (1) | Patents (1)
A whole-chip simulation methodology of the full ESD paths including the full-chip power and ground wiring network has been established, and successfully demonstrated on products with several hundreds of pins. By checking voltage stress across cross domain circuits itself, marginal cross domain ESD design window in sub-100nm SoCs can be extended.Show More

Cross domain protection analysis and verification using whole chip ESD simulation

Mototsugu Okushima;Tomohiro Kitayama;Susumu Kobayashi;Tetsuya Kato;Morihisa Hirata

Year: 2010 | Conference Paper |

A 4.5 kV HBM, 300 V CDM, 1.2 kV HMM ESD protected DC-to-16.1 GHz wideband LNA in 90 nm CMOS

D. Linten;S. Thijs;M. Okushima;M. Scholz;J. Borremans;M. Dehan;G. Groeseneken

2009 31st EOS/ESD Symposium
Year: 2009 | Conference Paper |
A DC-to-16.1 GHz wideband LNA in 90 nm digital CMOS is protected up to 4.5 kV HBM, equivalent 300 V CDM, and 1 kV HMM ESD stress by adding an area-efficient asymmetric T-diode with built-in local ESD protection in front of the RF input. Additional turn-off circuitry prevents any parasitic ESD path to be triggered in the core circuit.Show More

A 4.5 kV HBM, 300 V CDM, 1.2 kV HMM ESD protected DC-to-16.1 GHz wideband LNA in 90 nm CMOS

D. Linten;S. Thijs;M. Okushima;M. Scholz;J. Borremans;M. Dehan;G. Groeseneken

Year: 2009 | Conference Paper |

A DC-to-22 GHz 8.4mW compact dual-feedback wideband LNA in 90 nm digital CMOS

M. Okushima;J. Borremans;D. Linten;G. Groeseneken

2009 IEEE Radio Frequency Integrated Circuits Symposium
Year: 2009 | Conference Paper |
Cited by: Papers (18)
A dual-feedback topology to extend bandwidth of resistive feedback LNAs is proposed in this paper. Active source follower shunt-shunt feedback using a shunt peaking inductor to extend the 3-dB and input matching bandwidth is employed, combined with series-shunt feedback for extended impedance matching using a source inductor. A prototype in 90 nm digital CMOS achieves a high 3-dB bandwidth of 29 G...Show More

A DC-to-22 GHz 8.4mW compact dual-feedback wideband LNA in 90 nm digital CMOS

M. Okushima;J. Borremans;D. Linten;G. Groeseneken

Year: 2009 | Conference Paper |

Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications

S. Thijs;M. Okushima;J. Borremans;P. Jansen;D. Linten;M. Scholz;P. Wambacq;G. Groeseneken

2008 IEEE Custom Integrated Circuits Conference
Year: 2008 | Conference Paper |
Cited by: Papers (4)
Charged device model (CDM) electrostatic discharge (ESD) stress is a major concern for inductor-based ESD protection strategies for RF circuits processed in advanced nano-CMOS technologies. The CDM robustness of such protection methodology is investigated in this paper based on very-fast transmission line pulse (VFTLP) measurements. Its applicability is discussed for future technologies and RF app...Show More

Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications

S. Thijs;M. Okushima;J. Borremans;P. Jansen;D. Linten;M. Scholz;P. Wambacq;G. Groeseneken

Year: 2008 | Conference Paper |

Layout technique to alleviate soft failure for short pitch multi finger ESD protection devices

Mototsugu Okushima;Tsutomu Shinzaw;Yasuyuki Morishita

2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)
Year: 2007 | Conference Paper |
Cited by: Papers (4) | Patents (1)
This paper describes a layout technique to alleviate soft failure for short pitch multi finger ggMOS devices. Forming metal path parallel to the finger achieved 17-30% improvement in soft failure current without area penalty. Improvement of heat dissipation parallel to the finger is a possible explanation for this phenomenon.Show More

Layout technique to alleviate soft failure for short pitch multi finger ESD protection devices

Mototsugu Okushima;Tsutomu Shinzaw;Yasuyuki Morishita

Year: 2007 | Conference Paper |

Operation analysis and implementation of CMOS compatible vertical bipolar ESD protection devices for automotive applications

Mototsugu Okushima;Tsutomu Shinzawa

2006 Electrical Overstress/Electrostatic Discharge Symposium
Year: 2006 | Conference Paper |
In analysis of CMOS compatible vertical bipolar electrostatic discharge (ESD) protection, resistor avalanche breakdown in the collector region was identified as a dominant factor in ESD failure mechanism. The local high resistor has been formed near the surface because the collector electrode was fabricated with shared implantation of ultra-shallow source/drain implantation in 130 nm CMOS process....Show More

Operation analysis and implementation of CMOS compatible vertical bipolar ESD protection devices for automotive applications

Mototsugu Okushima;Tsutomu Shinzawa

Year: 2006 | Conference Paper |

ESD protection design for mixed-power domains in 90nm CMOS with new efficient power clamp and GND current trigger (GCT) technique

Mototsugu Okushima

2006 Electrical Overstress/Electrostatic Discharge Symposium
Year: 2006 | Conference Paper |
Cited by: Papers (4) | Patents (4)
This paper presents an ESD protection design scheme for mixed-power domains in narrow ESD design window with ultra-thin gate oxides. Using a grounded gate (gg)NMOS-based clamp with contact ballast (CTB) layout technique, a factor of 3X area reduction can be achieved for MM protection of a 1.6 nm gate oxide compared to a conventional silicide-block ESD scheme. To expand the design window, a novel g...Show More

ESD protection design for mixed-power domains in 90nm CMOS with new efficient power clamp and GND current trigger (GCT) technique

Mototsugu Okushima

Year: 2006 | Conference Paper |

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