Loading web-font TeX/Math/Italic
V. Delaye - IEEE Xplore Author Profile
Subscribe
ADVANCED SEARCH

Author details

< Back

V. Delaye

Also published under: Vincent Delaye

Publications
43
Citations
668
Publications by Year
20062018
Co-Authors:
Show All Co-Authors (348)
Image of author V. Delaye

V. Delaye

Also published under: Vincent Delaye

Affiliation

SERMA Technologie, Grenoble, France

Publication Topics

Biography

Vincent Delaye received the M.Sc. degree from Telecom Saint-Etienne, Saint-Étienne, France, and the Ph.D. degree from Grenoble INP, Grenoble, France, in 2000.,Since 2011, he has been managing the LETI competence center in electron microscopy within the platform for nanocharacterization at MINATEC Campus.(Based on document published on 21 September 2017).
Publications
43
Citations
668
Publications by Year
20062018
Co-Authors:
Show All Co-Authors (348)
Author's Published Works

Showing 1-25 of 43 results

  • Sort

Filter Results

Show

Sort By

Results

Tunability of Parasitic Channel in Gate-All-Around Stacked Nanosheets

S. Barraud;B. Previtali;V. Lapras;C. Vizioz;J.-M. Hartmann;S. Martinie;J. Lacord;M. Cassé;L. Dourthe;V. Loup;G. Romano;N. Rambal;Z. Chalupa;N. Bernier;G. Audoit;A. Jannaud;V. Delaye;V. Balan;O. Rozeau;T. Ernst;M. Vinet

2018 IEEE International Electron Devices Meeting (IEDM)
Year: 2018 | Conference Paper |
Cited by: Papers (32)
For the first time, a comprehensive study going from the integration of 3D stacked nanosheets Gate-All-Around (GAA) MOSFET devices to SPICE modeling is proposed. Devices have been successfully fabricated on SOI substrates using a replacement high-\kappa metal gate process and self-aligned-contacts. Back-biasing is herein efficiently used to highlight a drastic improvement of electrostatics in th...Show More

Tunability of Parasitic Channel in Gate-All-Around Stacked Nanosheets

S. Barraud;B. Previtali;V. Lapras;C. Vizioz;J.-M. Hartmann;S. Martinie;J. Lacord;M. Cassé;L. Dourthe;V. Loup;G. Romano;N. Rambal;Z. Chalupa;N. Bernier;G. Audoit;A. Jannaud;V. Delaye;V. Balan;O. Rozeau;T. Ernst;M. Vinet

Year: 2018 | Conference Paper |

Phase-Change Memory: Performance, Roles and Challenges

Gabriele Navarro;Guillaume Bourgeois;Julia Kluge;Anna Lisa Serra;Anthonin Verdy;Julien Garrione;Marie-Claire Cyrille;Nicolas Bernier;Audrey Jannaud;Chiara Sabbione;Mathieu Bernard;Emmanuel Nolot;Frederic Fillot;Pierre Noe;Leila Fellouh;Guillaume Rodriguez;Virginie Beugin;Olga Cueto;Niccole Castellani;Jean Coignus;Vincent Delaye;Carole Socquet-Clerc;Thomas Magis;Christelle Boixaderas;Sebastien Barnola;Etienne Nowak

2018 IEEE International Memory Workshop (IMW)
Year: 2018 | Conference Paper |
Cited by: Papers (12)
In this paper we analyze recent progress in Phase- Change Memory (PCM) technology targeting both Storage Class Memory and embedded applications. The challenge to achieve a high temperature data retention without compromising the device programming speed can be addressed by material engineering. We show that volume and thermal confinement improvement of the phase-change material enables a high (10-...Show More

Phase-Change Memory: Performance, Roles and Challenges

Gabriele Navarro;Guillaume Bourgeois;Julia Kluge;Anna Lisa Serra;Anthonin Verdy;Julien Garrione;Marie-Claire Cyrille;Nicolas Bernier;Audrey Jannaud;Chiara Sabbione;Mathieu Bernard;Emmanuel Nolot;Frederic Fillot;Pierre Noe;Leila Fellouh;Guillaume Rodriguez;Virginie Beugin;Olga Cueto;Niccole Castellani;Jean Coignus;Vincent Delaye;Carole Socquet-Clerc;Thomas Magis;Christelle Boixaderas;Sebastien Barnola;Etienne Nowak

Year: 2018 | Conference Paper |

Towards 500°C SPER activated devices for 3D sequential integration

J. Micout;B. Sklenard;P. Batude;R. Berthelon;Q. Rafhay;J. Lacord;B. Mathieu;L. Pasini;Z. Saghi;V. Delaye;L. Brunet;C. Fenouillet-Beranger;S. Joblot;F. Mazen;V. Mazzocchi;J-P. Colinge;G. Ghibaudo;M. Vinet

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
Year: 2017 | Conference Paper |
Cited by: Papers (1)
This work investigates the possibility to reduce the Solid Phase Epitaxy Regrowth (SPER) temperature for dopant activation needed in 3D sequential integration. The electrical results obtained on 28nm FDSOI devices show that 500°C SPER can yield similar performance to that of 600°C SPER and 1050°C spike anneal. This paper highlights the advantages of using a -oriented channel and tilted impla...Show More

Towards 500°C SPER activated devices for 3D sequential integration

J. Micout;B. Sklenard;P. Batude;R. Berthelon;Q. Rafhay;J. Lacord;B. Mathieu;L. Pasini;Z. Saghi;V. Delaye;L. Brunet;C. Fenouillet-Beranger;S. Joblot;F. Mazen;V. Mazzocchi;J-P. Colinge;G. Ghibaudo;M. Vinet

Year: 2017 | Conference Paper |

High performance low temperature FinFET with DSPER, gate last and Self Aligned Contact for 3D sequential mtegration

J. Micout;V. Lapras;P. Batude;C. Fenouillet-Beranger;J. Lacord;B. Sklenard;B. Mathieu;Q. Rafhay;V. Mazzocchi;J.-P. Colinge;L. Lachal;X. Garros;M. Casse;A. Toffoli;G. Romano;F. Allain;L. Brunet;J.-M. Hartmann;R. Bortolin;F. Mazen;S. Barraud;N. Rambal;C. Tabone;M.-P. Samson;P. Besombes;V. Delaye;Z. Saghi;V. Loup;C. Comboroure;V. Balan;L. Desvoivres;C. Vizioz;G. Ghibaudo;M. Vinet

2017 IEEE International Electron Devices Meeting (IEDM)
Year: 2017 | Conference Paper |
Cited by: Papers (5)
For the first time, a low temperature (LT) FinFET process is demonstrated, using Solid Phase Epitaxy Regrowth (SPER), gate last integration and Self Aligned Contact (SAC). The LT devices exhibit performances close to those of the High Temperature Process Of Reference (HT POR). Several techniques of SPER doping are investigated and an innovative Double SPER (DSPER) process using two amorphization/r...Show More

High performance low temperature FinFET with DSPER, gate last and Self Aligned Contact for 3D sequential mtegration

J. Micout;V. Lapras;P. Batude;C. Fenouillet-Beranger;J. Lacord;B. Sklenard;B. Mathieu;Q. Rafhay;V. Mazzocchi;J.-P. Colinge;L. Lachal;X. Garros;M. Casse;A. Toffoli;G. Romano;F. Allain;L. Brunet;J.-M. Hartmann;R. Bortolin;F. Mazen;S. Barraud;N. Rambal;C. Tabone;M.-P. Samson;P. Besombes;V. Delaye;Z. Saghi;V. Loup;C. Comboroure;V. Balan;L. Desvoivres;C. Vizioz;G. Ghibaudo;M. Vinet

Year: 2017 | Conference Paper |

CMOS-Compatible Contacts to n-InP

Elodie Ghegin;Philippe Rodriguez;Mattia Pasquali;Isabelle Sagnes;János L. Lábár;Vincent Delaye;Tiphaine Card;Jérémy Da Fonseca;Christophe Jany;Fabrice Nemouchi

IEEE Transactions on Electron Devices
Year: 2017 | Volume: 64, Issue: 11 | Journal Article |
Cited by: Papers (13)
In the context of the development of silicon photonics, various Ti- and Ni-based alloyed metallizations have been investigated for the purpose of forming low resistivity and Si CMOS-compatible contacts to n-InP. The innovative Ni2P metallization combined with an in situ Ar+ preclean represents the most suitable available solution for the formation of ohmic contacts with a specific contact resistiv...Show More

CMOS-Compatible Contacts to n-InP

Elodie Ghegin;Philippe Rodriguez;Mattia Pasquali;Isabelle Sagnes;János L. Lábár;Vincent Delaye;Tiphaine Card;Jérémy Da Fonseca;Christophe Jany;Fabrice Nemouchi

Year: 2017 | Volume: 64, Issue: 11 | Journal Article |

Key process steps for high performance and reliable 3D Sequential Integration

C.-M. V. Lu;F. Deprat;C. Fenouillet-Beranger;P. Batude;X. Garros;A. Tsiara;C. Leroux;R. Gassilloud;D. Nouguier;D. Ney;X. Federspiel;P. Besombes;A. Toffoli;G. Romano;N. Rambal;V. Delaye;D. Barge;M.-P. Samson;B. Previtali;C. Tabone;L. Pasini;L. Brunet;F. Andrieu;J. Micoud;T. Skotnicki;M. Vinet

2017 Symposium on VLSI Technology
Year: 2017 | Conference Paper |
Cited by: Papers (11)
This work provides breakthroughs in key technological modules for high performance and reliable 3D Sequential Integration with intermediate BEOL (iBEOL) in-between tiers. We demonstrate that (i) a high-quality solid phase epitaxy process is possible at 500°C, (ii) TiN native oxide removal prior to poly deposition leads to an improvement in gate stack reliability below 525°C and (iii) state-of-the-...Show More

Key process steps for high performance and reliable 3D Sequential Integration

C.-M. V. Lu;F. Deprat;C. Fenouillet-Beranger;P. Batude;X. Garros;A. Tsiara;C. Leroux;R. Gassilloud;D. Nouguier;D. Ney;X. Federspiel;P. Besombes;A. Toffoli;G. Romano;N. Rambal;V. Delaye;D. Barge;M.-P. Samson;B. Previtali;C. Tabone;L. Pasini;L. Brunet;F. Andrieu;J. Micoud;T. Skotnicki;M. Vinet

Year: 2017 | Conference Paper |

High performance CMOS FDSOI devices activated at low temperature

L. Pasini;P. Batude;J. Lacord;M. Casse;B. Mathieu;B. Sklenard;F. Piegas Luce;J. Micout;A. Payet;F. Mazen;P. Besson;E. Ghegin;J. Borrel;R. Daubriac;L. Hutin;D. Blachier;D. Barge;S. Chhun;V. Mazzocchi;A. Cros;J-P. Barnes;Z. Saghi;V. Delaye;N. Rambal;V. Lapras;J. Mazurier;O. Weber;F. Andrieu;L. Brunet;C. Fenouillet-Beranger;Q. Rafhay;G. Ghibaudo;F. Cristiano;M. Haond;F. Boeuf;M. Vinet

2016 IEEE Symposium on VLSI Technology
Year: 2016 | Conference Paper |
Cited by: Papers (13)
3D sequential integration requires top FETs processed with a low thermal budget (500–600°C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the introduction of mobility boosters (pMOS: SiGe 27% channel / SiGe:B 35% RSD and nMOS: SiC:P RSD). This first demonstration of n and p extension first FDSOI devices shows that ...Show More

High performance CMOS FDSOI devices activated at low temperature

L. Pasini;P. Batude;J. Lacord;M. Casse;B. Mathieu;B. Sklenard;F. Piegas Luce;J. Micout;A. Payet;F. Mazen;P. Besson;E. Ghegin;J. Borrel;R. Daubriac;L. Hutin;D. Blachier;D. Barge;S. Chhun;V. Mazzocchi;A. Cros;J-P. Barnes;Z. Saghi;V. Delaye;N. Rambal;V. Lapras;J. Mazurier;O. Weber;F. Andrieu;L. Brunet;C. Fenouillet-Beranger;Q. Rafhay;G. Ghibaudo;F. Cristiano;M. Haond;F. Boeuf;M. Vinet

Year: 2016 | Conference Paper |

First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers

L. Brunet;P. Batude;C. Fenouillet-Beranger;P. Besombes;L. Hortemel;F. Ponthenier;B. Previtali;C. Tabone;A. Royer;C. Agraffeil;C. Euvrard-Colnat;A. Seignard;C. Morales;F. Fournel;L. Benaissa;T. Signamarcheix;P. Besson;M. Jourdan;R. Kachtouli;V. Benevent;J.-M. Hartmann;C. Comboroure;N. Allouti;N. Posseme;C. Vizioz;C. Arvet;S. Barnola;S. Kerdiles;L. Baud;L. Pasini;C.-M. V. Lu;F. Deprat;A. Toffoli;G. Romano;C. Guedj;V. Delaye;F. Boeuf;O. Faynot;M. Vinet

2016 IEEE Symposium on VLSI Technology
Year: 2016 | Conference Paper |
For the first time, a full 3D CMOS over CMOS CoolCube™ integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain. Functional 3D inverters with either PMOS or NMOS on the top level are highlighted. Furthermore, Si layer transfer above a 28nm W Me...Show More

First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers

L. Brunet;P. Batude;C. Fenouillet-Beranger;P. Besombes;L. Hortemel;F. Ponthenier;B. Previtali;C. Tabone;A. Royer;C. Agraffeil;C. Euvrard-Colnat;A. Seignard;C. Morales;F. Fournel;L. Benaissa;T. Signamarcheix;P. Besson;M. Jourdan;R. Kachtouli;V. Benevent;J.-M. Hartmann;C. Comboroure;N. Allouti;N. Posseme;C. Vizioz;C. Arvet;S. Barnola;S. Kerdiles;L. Baud;L. Pasini;C.-M. V. Lu;F. Deprat;A. Toffoli;G. Romano;C. Guedj;V. Delaye;F. Boeuf;O. Faynot;M. Vinet

Year: 2016 | Conference Paper |

First integration of Ni0.9Co0.1 on pMOS transistors

F. Deprat;F. Nemouchi;C. Fenouillet-Beranger;M. Cassé;Ph. Rodriguez;B. Previtali;N. Rambal;V. Delaye;M. Haond;M. Mellier;M. Gregoire;M. Danielou;S. Favier;P. Batude;M. Vinet

2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC)
Year: 2016 | Conference Paper |
Cited by: Papers (2)
In 3D sequential integration, the top transistor thermal budget must be reduced to preserve bottom MOSFET performance. In order to relax this thermal budget limitation, the thermal stability of the bottom level must be increased, especially for the silicide. In that purpose, Ni0.9Co0.1 alloy is proposed to replace the current Ni0.85Pt0.15 silicide. For the first time, this Ni0.9Co0.1 salicide has ...Show More

First integration of Ni0.9Co0.1 on pMOS transistors

F. Deprat;F. Nemouchi;C. Fenouillet-Beranger;M. Cassé;Ph. Rodriguez;B. Previtali;N. Rambal;V. Delaye;M. Haond;M. Mellier;M. Gregoire;M. Danielou;S. Favier;P. Batude;M. Vinet

Year: 2016 | Conference Paper |

Detecting Unintended Schottky Junctions and Their Impact on Tunnel FET Characteristics

Louis Hutin;Cyrille Le Royer;Robert Pierce Oeflein;Sébastien Martinie;Julien Borrel;Vincent Delaye;Jean-Michel Hartmann;Claude Tabone;Maud Vinet

IEEE Transactions on Electron Devices
Year: 2016 | Volume: 63, Issue: 6 | Journal Article |
Cited by: Papers (6)
We demonstrate in this paper a fast and simple method for evidencing and classifying the ambipolar response of tunneling-based field effect transistors in pull-down (nFET-like) and pull-up (pFET-like) modes. This technique enables to unequivocally determine whether carrier injection on either side of the device occurs via band-to-band-tunneling or single carrier tunneling through a Schottky barrie...Show More

Detecting Unintended Schottky Junctions and Their Impact on Tunnel FET Characteristics

Louis Hutin;Cyrille Le Royer;Robert Pierce Oeflein;Sébastien Martinie;Julien Borrel;Vincent Delaye;Jean-Michel Hartmann;Claude Tabone;Maud Vinet

Year: 2016 | Volume: 63, Issue: 6 | Journal Article |

Investigation of the potentialities of Vertical Resistive RAM (VRRAM) for neuromorphic applications

G. Piccolboni;G. Molas;J. M. Portal;R. Coquand;M. Bocquet;D. Garbin;E. Vianello;C. Carabasse;V. Delaye;C. Pellissier;T. Magis;C. Cagli;M. Gely;O. Cueto;D. Deleruyelle;G. Ghibaudo;B. De Salvo;L. Perniola

2015 IEEE International Electron Devices Meeting (IEDM)
Year: 2015 | Conference Paper |
Cited by: Papers (21)
Combining Resistive RAM concept with Vertical NAND technology and design, Vertical RRAM (VRRAM) was recently proposed as a cost-effective and extensible technology for future mass data storage applications [1]. 3D RRAM based neural networks were also proposed to emulate the potentiation and depression of a synapse [2], but more complex circuits were not discussed. In previous works [3-4], various ...Show More

Investigation of the potentialities of Vertical Resistive RAM (VRRAM) for neuromorphic applications

G. Piccolboni;G. Molas;J. M. Portal;R. Coquand;M. Bocquet;D. Garbin;E. Vianello;C. Carabasse;V. Delaye;C. Pellissier;T. Magis;C. Cagli;M. Gely;O. Cueto;D. Deleruyelle;G. Ghibaudo;B. De Salvo;L. Perniola

Year: 2015 | Conference Paper |

Investigation of Forming, SET, and Data Retention of Conductive-Bridge Random-Access Memory for Stack Optimization

Jérémy Guy;Gabriel Molas;Philippe Blaise;Mathieu Bernard;Anne Roule;Gilles Le Carval;Vincent Delaye;Alain Toffoli;Gérard Ghibaudo;Fabien Clermidy;Barbara De Salvo;Luca Perniola

IEEE Transactions on Electron Devices
Year: 2015 | Volume: 62, Issue: 11 | Journal Article |
Cited by: Papers (45)
In this paper, we investigate in depth Forming, SET, and Retention of conductive-bridge random-access memory (CBRAM). A kinetic Monte Carlo model of the CBRAM has been developed considering ionic hopping and chemical reaction dynamics. Based on inputs from ab initio calculations and the physical properties of the materials, the model offers the simulation of both the Forming/SET and the Data Reten...Show More

Investigation of Forming, SET, and Data Retention of Conductive-Bridge Random-Access Memory for Stack Optimization

Jérémy Guy;Gabriel Molas;Philippe Blaise;Mathieu Bernard;Anne Roule;Gilles Le Carval;Vincent Delaye;Alain Toffoli;Gérard Ghibaudo;Fabien Clermidy;Barbara De Salvo;Luca Perniola

Year: 2015 | Volume: 62, Issue: 11 | Journal Article |

Investigation of HfO2/Ti based vertical RRAM - Performances and variability

G. Piccolboni;G. Molas;C. Carabasse;J. F. Nodin;C. Pellissier;P. Brianceau;E. Vianello;O. Pollet;F. Perrin;J. Cluzel;A. Toffoli;F. Aussenac;V. Delaye;G. Ghibaudo;B. De Salvo;L. Perniola

2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)
Year: 2014 | Conference Paper |
Cited by: Papers (3) | Patents (1)
An easy-to-fabricate, low-cost, sidewall TiN/HfO2/Ti vertical resistive RAM (VRRAM) device is proposed. Devices with bottom electrode thickness down to 10nm were fabricated and characterized. Forming, SET and RESET voltages of respectively 2V, 0.5V and -0.5V were measured. A stable memory window of one decade was maintained after 105s at 200°C. The impact of scaling on the operating voltages and m...Show More

Investigation of HfO2/Ti based vertical RRAM - Performances and variability

G. Piccolboni;G. Molas;C. Carabasse;J. F. Nodin;C. Pellissier;P. Brianceau;E. Vianello;O. Pollet;F. Perrin;J. Cluzel;A. Toffoli;F. Aussenac;V. Delaye;G. Ghibaudo;B. De Salvo;L. Perniola

Year: 2014 | Conference Paper |

High performance polysilicon nanowire NEMS for CMOS embedded nanosensors

I. Ouerghi;J. Philippe;L. Duraffourg;L. Laurent;A. Testini;K. Benedetto;A. M. Charvet;V. Delaye;L. Masarotto;P. Scheiblin;C. Reita;K. Yckache;C. Ladner;W. Ludurczak;T. Ernst

2014 IEEE International Electron Devices Meeting
Year: 2014 | Conference Paper |
Cited by: Papers (8)
We present for the first time sub-100nm poly-Silicon nanowire (poly-Si NW) based NEMS resonators for low cost cointegrated mass sensors on CMOS featuring excellent performance when compared to crystalline silicon. In particular, comparable quality factors (130 in the air, 3900 in vacuum) and frequency stabilities are demonstrated. The minimum measured Allan deviation of 7×10-7 leads to a mass reso...Show More

High performance polysilicon nanowire NEMS for CMOS embedded nanosensors

I. Ouerghi;J. Philippe;L. Duraffourg;L. Laurent;A. Testini;K. Benedetto;A. M. Charvet;V. Delaye;L. Masarotto;P. Scheiblin;C. Reita;K. Yckache;C. Ladner;W. Ludurczak;T. Ernst

Year: 2014 | Conference Paper |

Experimental and theoretical understanding of Forming, SET and RESET operations in Conductive Bridge RAM (CBRAM) for memory stack optimization

J. Guy;G. Molas;P. Blaise;C. Carabasse;M. Bernard;A. Roule;G. Le Carval;V. Sousa;H. Grampeix;V. Delaye;A. Toffoli;J. Cluzel;P. Brianceau;O. Pollet;V. Balan;S. Barraud;O. Cueto;G. Ghibaudo;F. Clermidy;B. De Salvo;L. Perniola

2014 IEEE International Electron Devices Meeting
Year: 2014 | Conference Paper |
Cited by: Papers (21)
In this paper, we deeply investigate for the 1st time at our knowledge the impact of the CBRAM memory stack on the Forming, SET and RESET operations. Kinetic Monte Carlo simulations, based on inputs from ab-initio calculations and taking into account ionic hopping and chemical reaction dynamics are used to analyse experimental results obtained on decananometric devices. We propose guidelines to op...Show More

Experimental and theoretical understanding of Forming, SET and RESET operations in Conductive Bridge RAM (CBRAM) for memory stack optimization

J. Guy;G. Molas;P. Blaise;C. Carabasse;M. Bernard;A. Roule;G. Le Carval;V. Sousa;H. Grampeix;V. Delaye;A. Toffoli;J. Cluzel;P. Brianceau;O. Pollet;V. Balan;S. Barraud;O. Cueto;G. Ghibaudo;F. Clermidy;B. De Salvo;L. Perniola

Year: 2014 | Conference Paper |

Top-Down Fabrication of Epitaxial SiGe/Si Multi-(Core/Shell) p-FET Nanowire Transistors

Sylvain Barraud;Jean-Michel Hartmann;Virginie Maffini-Alvaro;Lucie Tosti;Vincent Delaye;Dominique Lafond

IEEE Transactions on Electron Devices
Year: 2014 | Volume: 61, Issue: 4 | Journal Article |
Cited by: Papers (17)
Short-gate length epitaxial Si1-xGex/Si multi-(core/shell) p-type nanowire (NW) transistors with high-permittivity dielectric and metal gate were fabricated and their electrical properties examined. Silicon NWs were first of all patterned in ultrathin silicon-on-insulator wafers by lithography and etching. Selective epitaxial growth of Si0.7Ge0.3/Si or Si0.7Ge0.3/Si/Si0.7Ge0.3/Si shells was then p...Show More

Top-Down Fabrication of Epitaxial SiGe/Si Multi-(Core/Shell) p-FET Nanowire Transistors

Sylvain Barraud;Jean-Michel Hartmann;Virginie Maffini-Alvaro;Lucie Tosti;Vincent Delaye;Dominique Lafond

Year: 2014 | Volume: 61, Issue: 4 | Journal Article |

Trade-off between SET and data retention performance thanks to innovative materials for phase-change memory

G. Navarro;M. Coué;A. Kiouseloglou;P. Noé;F. Fillot;V. Delaye;A. Persico;A. Roule;M. Bernard;C. Sabbione;D. Blachier;V. Sousa;L. Perniola;S. Maitrejean;A. Cabrini;G. Torelli;P. Zuliani;R. Annunziata;E. Palumbo;M. Borghi;G. Reimbold;B. De Salvo

2013 IEEE International Electron Devices Meeting
Year: 2013 | Conference Paper |
In this paper, we investigate the impact of Ge-enrichment coupled to N- or C-doping in Ge2Sb2Te5 based materials on low-resistance state (LRS or SET) performance combined with high-resistance state (HRS or RESET) high-temperature data retention (HTDR) in Phase-Change Memories (PCM). These innovative materials have been integrated in state-of-the-art memory cell prototypes. For the first time, a fo...Show More

Trade-off between SET and data retention performance thanks to innovative materials for phase-change memory

G. Navarro;M. Coué;A. Kiouseloglou;P. Noé;F. Fillot;V. Delaye;A. Persico;A. Roule;M. Bernard;C. Sabbione;D. Blachier;V. Sousa;L. Perniola;S. Maitrejean;A. Cabrini;G. Torelli;P. Zuliani;R. Annunziata;E. Palumbo;M. Borghi;G. Reimbold;B. De Salvo

Year: 2013 | Conference Paper |

Reliability study of carbon-doped GST stack robust against Pb-free soldering reflow

S. Souiki;Q. Hubert;G. Navarro;A. Persico;C. Jahan;E. Henaff;V. Delaye;D. Blachier;V. Sousa;L. Perniola;E. Vianello;B. De Salvo

2013 IEEE International Reliability Physics Symposium (IRPS)
Year: 2013 | Conference Paper |
Cited by: Papers (2)
In this paper, we investigate the performances of carbon-doped Ge2Sb2Te5 films (named hereafter GST) which have been integrated together with a thin titanium capping layer into Phase-Change Memory devices. We show that the carbon content into GST and the titanium cap layer thickness can be optimized to obtain an Amorphous As-Deposited (A-AD) phase which is stable under both the typical Back End-Of...Show More

Reliability study of carbon-doped GST stack robust against Pb-free soldering reflow

S. Souiki;Q. Hubert;G. Navarro;A. Persico;C. Jahan;E. Henaff;V. Delaye;D. Blachier;V. Sousa;L. Perniola;E. Vianello;B. De Salvo

Year: 2013 | Conference Paper |

Detailed Analysis of the Role of Thin-${\rm HfO}_{2}$ Interfacial Layer in ${\rm Ge}_{2}{\rm Sb}_{2}{\rm Te}_{5}$-Based PCM

Quentin Hubert;Carine Jahan;Alain Toffoli;Vincent Delaye;Dominique Lafond;Helen Grampeix;Barbara de Salvo

IEEE Transactions on Electron Devices
Year: 2013 | Volume: 60, Issue: 7 | Journal Article |
Cited by: Papers (11)
In this paper, we show that performances of Ge2Sb2Te5-based phase-change memory (PCM) cells can be improved by the insertion of a thin HfO2 interfacial layer between the phase-change material and the tungsten plug. Significant reduction of the RESET and SET currents and of the energy required to switch the PCM cells are demonstrated. In addition, compared with pure GST reference cells, the presenc...Show More

Detailed Analysis of the Role of Thin-${\rm HfO}_{2}$ Interfacial Layer in ${\rm Ge}_{2}{\rm Sb}_{2}{\rm Te}_{5}$-Based PCM

Quentin Hubert;Carine Jahan;Alain Toffoli;Vincent Delaye;Dominique Lafond;Helen Grampeix;Barbara de Salvo

Year: 2013 | Volume: 60, Issue: 7 | Journal Article |

Sb-doped GeS2 as performance and reliability booster in Conductive Bridge RAM

E. Vianello;G. Molas;F. Longnos;P. Blaise;E. Souchier;C. Cagli;G. Palma;J. Guy;M. Bernard;M. Reyboz;G. Rodriguez;A. Roule;C. Carabasse;V. Delaye;V. Jousseaume;S. Maitrejean;G. Reimbold;B. De Salvo;F. Dahmani;P. Verrier;D. Bretegnier;J. Liebault

2012 International Electron Devices Meeting
Year: 2012 | Conference Paper |
Cited by: Papers (21)
In this work, for the first time at our knowledge, the improvement of chalcogenide-based CBRAM performance and reliability by Sb doping of the GeS2 electrolyte is presented. An original analysis, based on in-depth physico-chemical characterization, device electrical measurements, empirical model and first principle calculations, is shown. We argue that optimized ~10% Sb doping in the GeS2 electrol...Show More

Sb-doped GeS2 as performance and reliability booster in Conductive Bridge RAM

E. Vianello;G. Molas;F. Longnos;P. Blaise;E. Souchier;C. Cagli;G. Palma;J. Guy;M. Bernard;M. Reyboz;G. Rodriguez;A. Roule;C. Carabasse;V. Delaye;V. Jousseaume;S. Maitrejean;G. Reimbold;B. De Salvo;F. Dahmani;P. Verrier;D. Bretegnier;J. Liebault

Year: 2012 | Conference Paper |

Ti impact in C-doped phase-change memories compliant to Pb-free soldering reflow

L. Perniola;P. Noé;Q. Hubert;S. Souiki;G. Ghezzi;G. Navarro;A. Cabrini;A. Persico;V. Delaye;D. Blachier;J.-P. Barnes;E. Henaff;M. Tessaire;E. Souchier;A. Roule;F. Fillot;J. Ferrand;A. Fargeix;F. Hippert;J.-Y. Raty;C. Jahan;V. Sousa;G. Torelli;S. Maitrejean;B. De Salvo;G. Reimbold

2012 International Electron Devices Meeting
Year: 2012 | Conference Paper |
Cited by: Papers (6) | Patents (1)
In this paper, we present a thorough physical-chemical analysis of an engineered PCM stack, where the integration of C-doping and the use of a Ti top layer allow obtaining an Amorphous As-Deposited (A-AD) phase stable against Back End-Of-Line (BEOL) thermal budget. This PCM stack is then integrated in devices, which are extensively tested in order to validate a novel pre-coding technique compliant...Show More

Ti impact in C-doped phase-change memories compliant to Pb-free soldering reflow

L. Perniola;P. Noé;Q. Hubert;S. Souiki;G. Ghezzi;G. Navarro;A. Cabrini;A. Persico;V. Delaye;D. Blachier;J.-P. Barnes;E. Henaff;M. Tessaire;E. Souchier;A. Roule;F. Fillot;J. Ferrand;A. Fargeix;F. Hippert;J.-Y. Raty;C. Jahan;V. Sousa;G. Torelli;S. Maitrejean;B. De Salvo;G. Reimbold

Year: 2012 | Conference Paper |

Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10nm Width

R. Coquand;M. Cassé;S. Barraud;P. Leroux;D. Cooper;C. Vizioz;C. Comboroure;P. Perreau;V. Maffini-Alvaro;C. Tabone;L. Tosti;F. Allain;S. Barnola;V. Delaye;F. Aussenac;G. Reimbold;G. Ghibaudo;D. Munteanu;S. Monfray;F. Boeuf;O. Faynot;T. Poiroux

2012 Symposium on VLSI Technology (VLSIT)
Year: 2012 | Conference Paper |
Cited by: Papers (24)
A detailed study of performance in uniaxially-strained Si nanowire (NW) transistors fabricated by lateral strain relaxation of biaxial SSOI substrate is presented. 2D strain imaging demonstrates the lateral strain relaxation resulting from nanoscale patterning. For the first time, an improvement of electron mobility in SSOI NW scaled down to 10nm width has been successfully demonstrated (+55% with...Show More

Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10nm Width

R. Coquand;M. Cassé;S. Barraud;P. Leroux;D. Cooper;C. Vizioz;C. Comboroure;P. Perreau;V. Maffini-Alvaro;C. Tabone;L. Tosti;F. Allain;S. Barnola;V. Delaye;F. Aussenac;G. Reimbold;G. Ghibaudo;D. Munteanu;S. Monfray;F. Boeuf;O. Faynot;T. Poiroux

Year: 2012 | Conference Paper |

Physical Understanding of Program Injection and Consumption in Ultra-Scaled SiN Split-Gate Memories

L. Masoero;G. Molas;V. Della Marca;M. Gely;O. Cueto;J. P. Colonna;A. De Luca;P. Brianceau;C. Charpin;D. Lafond;V. Delaye;F. Aussenac;C. Carabasse;S. Pauliac;C. Comboroure;P. Boivin;G. Ghibaudo;S. Deleonibus;B. De Salvo

2012 4th IEEE International Memory Workshop
Year: 2012 | Conference Paper |
Cited by: Papers (3)
In this work, a detailed study of the physical mechanisms governing the Source Side Injection programming in ultra-scaled (down to 20nm) SiN split-gate memories is presented. Experimental measurements coupled to static and dynamic TCAD simulations are shown. In particular, we claim that adjusting the select gate voltage in moderate inversion allows for the optimization of the compromise between hi...Show More

Physical Understanding of Program Injection and Consumption in Ultra-Scaled SiN Split-Gate Memories

L. Masoero;G. Molas;V. Della Marca;M. Gely;O. Cueto;J. P. Colonna;A. De Luca;P. Brianceau;C. Charpin;D. Lafond;V. Delaye;F. Aussenac;C. Carabasse;S. Pauliac;C. Comboroure;P. Boivin;G. Ghibaudo;S. Deleonibus;B. De Salvo

Year: 2012 | Conference Paper |

Investigation of the Electrical Performances of µtrench PCM at High Operating Temperature

G. Navarro;S. Souiki;A. Persico;V. Sousa;J.-F. Nodin;C. Jahan;F. Aussenac;V. Delaye;O. Cueto;L. Perniola;B. De Salvo

2012 4th IEEE International Memory Workshop
Year: 2012 | Conference Paper |
In this paper, we investigate the electrical performance of Phase-Change Memory (PCM) devices at high operating temperature (up to 180°C). We perform a detailed experimental analysis on μtrench PCM cells with different dimensions. We show that the high temperature strongly impacts the programming curves, by linearly decreasing the threshold voltage and decreasing the RESET current. Furthermore, th...Show More

Investigation of the Electrical Performances of µtrench PCM at High Operating Temperature

G. Navarro;S. Souiki;A. Persico;V. Sousa;J.-F. Nodin;C. Jahan;F. Aussenac;V. Delaye;O. Cueto;L. Perniola;B. De Salvo

Year: 2012 | Conference Paper |

IEEE Account

Purchase Details

Profile Information

Need Help?

A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.
© Copyright 2025 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.