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No Rush in Executing Atomic Instructions
Ashkan Asgharzadeh;Josué Feliu;Manuel E. Acacio;Stefanos Kaxiras;Alberto Ros
2025 IEEE International Symposium on High Performance Computer Architecture (HPCA)
Year: 2025 | Conference Paper |
Hardware atomic instructions are the building blocks of the synchronization algorithms. Historically, to guarantee atomicity and consistency, they were implemented using memory fences, committing older memory instructions, and draining the store buffer before initiating the execution of atomics. Unfortunately, the use of such memory fences entails huge performance penalties as it implies execution...Show More
Hardware Cache Locking for All Memory Updates
Ashkan Asgharzadeh;Eduardo José Gómez-Hernández;Juan M. Cebrian;Stefanos Kaxiras;Alberto Ros
2024 IEEE 42nd International Conference on Computer Design (ICCD)
Year: 2024 | Conference Paper |
Cited by: Papers (1)
Many applications need to perform operations that involve reading a value from memory, modifying it, and then writing it back. Multiple architectures provide hardware support for these operations via read-modify-write (RMW) instructions. The primary benefit is that the read can request a cacheline with write permissions, reducing coherence protocol overhead since the write will find the cacheline ...Show More
JANUS: A Simple and Efficient Speculative Defense using Reinforcement Learning
2024 IEEE 36th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)
Year: 2024 | Conference Paper |
Speculative execution and the emergence of Spectre attacks have forced architects to rethink how microprocessors are designed. Several approaches aim to close this security vulnerability while trying to minimize performance degradation, often involving complex and sophisticated mechanisms. These strategies typically entail substantial modifications to the processor core and memory hierarchy, which...Show More
TangramFP: Energy-Efficient, Bit-Parallel, Multiply-Accumulate for Deep Neural Networks
2024 IEEE 36th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)
Year: 2024 | Conference Paper |
As energy consumption becomes a primary concern for deep learning acceleration, the need to optimize not only data movement but also compute is becoming important. The basic element of compute, the Multiply-Accumulate (MAC) unit, performs the operation X · Y+Z, comprises the compute cores of systolic arrays such as Google’s TPU or Nvidia’s Tensor Cores, and it is found in practically every deep ne...Show More
A First Exploration of Fine-Grain Coherence for Integrity Metadata
Per Ekemark;Alberto Ros;Konstantinos Sagonas;Stefanos Kaxiras
2024 International Symposium on Secure and Private Execution Environment Design (SEED)
Year: 2024 | Conference Paper |
Memory integrity protection is intended for secure execution, and it is typically associated with programs running on a single core. However, with the emergence of multi-processor systems-on-chip and chiplets, extending memory integrity protection to cache-coherent multiprocessors becomes essential. In this work, we explore for the first time the design space for maintaining coherence in fine-grai...Show More
ReCon: Efficient Detection, Management, and Use of Non-Speculative Information Leakage
Pavlos Aimoniotis;Amund Bergland Kvalsvik;Xiaoyue Chen;Magnus Själander;Stefanos Kaxiras
2023 56th IEEE/ACM International Symposium on Microarchitecture (MICRO)
Year: 2023 | Conference Paper |
Cited by: Papers (1)
In a speculative side-channel attack, a secret is improperly accessed and then leaked by passing it to a transmitter instruction. Several proposed defenses effectively close this security hole by either delaying the secret from being loaded or propagated, or by delaying dependent transmitters (e.g., loads) from executing when fed with tainted input derived from an earlier speculative load. This re...Show More
How addresses are made
2023 IEEE International Symposium on Workload Characterization (IISWC)
Year: 2023 | Conference Paper |
This work uses Dynamic Information Flow Tracking (DIFT) to characterize how memory addresses are made by studying the transformation of data values into memory addresses. We show that in SPEC CPU 2017 benchmarks, a high proportion of values in memory are transformed into memory addresses. The majority of the transformations are done directly without explicit arithmetic instructions. Most of the ad...Show More
Splash-4: A Modern Benchmark Suite with Lock-Free Constructs
Eduardo José Gómez-Hernández;Juan M. Cebrian;Stefanos Kaxiras;Alberto Ros
2022 IEEE International Symposium on Workload Characterization (IISWC)
Year: 2022 | Conference Paper |
Cited by: Papers (3)
The cornerstone for the performance evaluation of computer systems is the benchmark suite. Among the many benchmark suites used in high-performance computing and multicore research, Splash-2 has been instrumental in advancing knowledge for both academia and industry. Published in 1995 and with over 5276 citations and counting, this benchmark suite is still in use to evaluate novel architectural pr...Show More
Data-Out Instruction-In (DOIN!): Leveraging Inclusive Caches to Attack Speculative Delay Schemes
Pavlos Aimoniotis;Amund Bergland Kvalsvik;Magnus Själander;Stefanos Kaxiras
2022 IEEE International Symposium on Secure and Private Execution Environment Design (SEED)
Year: 2022 | Conference Paper |
Cited by: Papers (3)
Although the cache has been a known side-channel for years, it has gained renewed notoriety with the introduction of speculative side-channel attacks such as Spectre, which were able to use caches to not just observe a victim, but to leak secrets. Because the cache continues to be one of the most exploitable side channels, it is often the primary target to safeguard in secure speculative execution...Show More
Do Not Predict – Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation
Christos Sakalis;Zamshed I. Chowdhury;Shayne Wadle;Ismail Akturk;Alberto Ros;Magnus Själander;Stefanos Kaxiras;Ulya R. Karpuzcu
2021 International Symposium on Secure and Private Execution Environment Design (SEED)
Year: 2021 | Conference Paper |
Cited by: Papers (2)
Recent architectural approaches that address speculative side-channel attacks aim to prevent software from exposing the microarchitectural state changes of transient execution. The Delay-on-Miss technique is one such approach, which simply delays loads that miss in the L1 cache until they become non-speculative, resulting in no transient changes in the memory hierarchy. However, this costs perform...Show More
Seeds of SEED: Preventing Priority Inversion in Instruction Scheduling to Disrupt Speculative Interference
2021 International Symposium on Secure and Private Execution Environment Design (SEED)
Year: 2021 | Conference Paper |
Cited by: Papers (3)
Speculative side-channel attacks consist of two parts: The speculative instructions that abuse speculative execution to gain illegal access to sensitive data and the side-channel instructions that leak the sensitive data. Typically, the side-channel instructions are assumed to follow the speculative instructions and be dependent on them. Speculative side-channel defenses have taken advantage of th...Show More
Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions
Pavlos Aimoniotis;Christos Sakalis;Magnus Själander;Stefanos Kaxiras
IEEE Computer Architecture Letters
Cited by: Papers (7)
Speculative side-channel attacks access sensitive data and use transmitters to leak the data during wrong-path execution. Various defenses have been proposed to prevent such information leakage. However, not all speculatively executed instructions are unsafe: Recent work demonstrates that speculation invariantinstructions are independent of speculative control-flow paths and are guaranteed to even...Show More
Splash-4: Improving Scalability with Lock-Free Constructs
Eduardo José Gómez-Hernández;Ruixiang Shao;Christos Sakalis;Stefanos Kaxiras;Alberto Ros
2021 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
Year: 2021 | Conference Paper |
Cited by: Papers (2)
Over the past three decades, the parallel applications of the Splash-2 benchmark suite have been instrumental in advancing multiprocessor research. Recently, the Splash-3 benchmarks eliminated performance bugs, data races, and improper synchronization that plagued Splash-2 benchmarks after the definition of the C memory model. In this work, we revisit the Splash-3 benchmarks and adapt them for con...Show More
TSOPER: Efficient Coherence-Based Strict Persistency
Per Ekemark;Yuan Yao;Alberto Ros;Konstantinos Sagonas;Stefanos Kaxiras
2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
Year: 2021 | Conference Paper |
Cited by: Papers (7)
We propose a novel approach for hardware-based strict TSO persistency, called TSOPER. We allow a TSO persistency model to freely coalesce values in the caches, by forming atomic groups of cachelines to be persisted. A group persist is initiated for an atomic group if any of its newly written values are exposed to the outside world. A key difference with prior work is that our architecture is based...Show More
Boosting Store Buffer Efficiency with Store-Prefetch Bursts
2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
Year: 2020 | Conference Paper |
Cited by: Papers (2)
Virtually all processors today employ a store buffer (SB) to hide store latency. However, when the store buffer is full, store latency is exposed to the processor causing pipeline stalls. The default strategies to mitigate these stalls are to issue prefetch for ownership requests when store instructions commit and to continuously increase the store buffer size. While these strategies considerably ...Show More
Speculative Enforcement of Store Atomicity
2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
Year: 2020 | Conference Paper |
Cited by: Papers (2)
Various memory consistency model implementations (e.g., x86, SPARC) willfully allow a core to see its own stores while they are in limbo, i.e., executed (and perhaps retired) but not yet inserted in memory order. This is known as store-to-load forwarding and it is a necessity to safeguard the local thread's sequential program semantics while achieving high performance. However, this can lead to co...Show More
Understanding Selective Delay as a Method for Efficient Secure Speculative Execution
Christos Sakalis;Stefanos Kaxiras;Alberto Ros;Alexandra Jimborean;Magnus Själander
IEEE Transactions on Computers
Cited by: Papers (11)
Since the introduction of Meltdown and Spectre, the research community has been tirelessly working on speculative side-channel attacks and on how to shield computer systems from them. To ensure that a system is protected not only from all the currently known attacks but also from future, yet to be discovered, attacks, the solutions developed need to be general in nature, covering a wide array of s...Show More
Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors
Mehdi Alipour;Stefanos Kaxiras;David Black-Schaffer;Rakesh Kumar
2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)
Year: 2020 | Conference Paper |
Cited by: Papers (11)
Flexible instruction scheduling is essential for performance in out-of-order processors. This is typically achieved by using CAM-based Instruction Queues (IQs) that provide complete flexibility in choosing ready instructions for execution, but at the cost of significant scheduling energy. In this work we seek to reduce the instruction scheduling energy by reducing the depth and width of the IQ. We...Show More
Filter Caching for Free: The Untapped Potential of the Store-Buffer
Ricardo Alves;Alberto Ros;David Black-Schaffer;Stefanos Kaxiras
2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA)
Year: 2019 | Conference Paper |
Cited by: Papers (3)
Modern processors contain store-buffers to allow stores to retire under a miss, thus hiding store-miss latency. The store-buffer needs to be large (for performance) and searched on every load (for correctness), thereby making it a costly structure in both area and energy. Yet on every load, the store-buffer is probed in parallel with the L1 and TLB, with no concern for the store-buffer's intrinsic...Show More
Efficient Invisible Speculative Execution through Selective Delay and Value Prediction
Christos Sakalis;Stefanos Kaxiras;Alberto Ros;Alexandra Jimborean;Magnus Själander
2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA)
Year: 2019 | Conference Paper |
Cited by: Papers (8)
Speculative execution, the base on which modern high-performance general-purpose CPUs are built on, has recently been shown to enable a slew of security attacks. All these attacks are centered around a common set of behaviors: During speculative execution, the architectural state of the system is kept unmodified, until the speculation can be verified. In the event that a misspeculation occurs, the...Show More
FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors
Mehdi Alipour;Rakesh Kumar;Stefanos Kaxiras;David Black-Schaffer
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Year: 2019 | Conference Paper |
Cited by: Papers (8)
The number of instructions a processor's instruction queue can examine (depth) and the number it can issue together (width) determine its ability to take advantage of the ILP in an application. Unfortunately, increasing either the width or depth of the instruction queue is very costly due to the content-addressable logic needed to wakeup and select instructions out-of-order. This work makes the ob...Show More
Dynamically Disabling Way-prediction to Reduce Instruction Replay
2018 IEEE 36th International Conference on Computer Design (ICCD)
Year: 2018 | Conference Paper |
Cited by: Papers (6)
Way-predictors have long been used to reduce dynamic cache energy without the performance loss of serial caches. However, they produce variable-latency hits, as incorrect predictions increase load-to-use latency. While the performance impact of these extra cycles has been well-studied, the need to replay subsequent instructions in the pipeline due to the load latency increase has been ignored. In ...Show More
The Superfluous Load Queue
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
Year: 2018 | Conference Paper |
In an out-of-order core, the load queue (LQ), the store queue (SQ), and the store buffer (SB) are responsible for ensuring: i) correct forwarding of stores to loads and ii) correct ordering among loads (with respect to external stores). The first requirement safeguards the sequential semantics of program execution and applies to both serial and parallel code; the second requirement safeguards the ...Show More
Non-Speculative Store Coalescing in Total Store Order
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA)
Year: 2018 | Conference Paper |
Cited by: Papers (10)
We present a non-speculative solution for a coalescing store buffer in total store order (TSO) consistency. Coalescing violates TSO with respect to both conflicting loads and conflicting stores, if partial state is exposed to the memory system. Proposed solutions for coalescing in TSO resort to speculation-and-rollback or centralized arbitration to guarantee atomicity for the set of stores whose o...Show More
Non-speculative load reordering in total store ordering
Stefanos Kaxiras;Trevor E. Carlson;Mehdi Alipour;Alberto Ros
Load reordering is important for performance. It allows a core to continue performing accesses to the memory system even when there are older, in-program-order, unperformed accesses (for example, due to long latency misses). The only known solution to allow such reordering in a strong consistency model such as total store ordering (TSO) has been to reorder speculatively and squash-and-re-execute i...Show More
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