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Woorham Bae - IEEE Xplore Author Profile

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Author details

Woorham Bae

Also published under: W. Bae, Woo-Rham Bae

Publications

50

Citations

581

Publications by Year

20142024

Co-Authors:

Elad AlonErik AndersonShahab ArdalanKrste AsanovićJonathan Bachrach

Show All Co-Authors (119)

Woorham Bae

Also published under: W. Bae, Woo-Rham Bae

Affiliation

Ayar Labs Inc, CA, USA

Publication Topics

Clock Frequency,
Neural Network,
Phase-locked Loop,
Reference Clock,
16-nm FinFET,
Additional Calibration,
Advanced Design,
Analog-to-digital Converter,
Asynchronous Sampling,
Bit Error Rate,
Boolean Logic,
Charge Pump

Biography

Woorham Bae (S’14–M’16) received the B.S. and Ph.D. degrees in electrical and computer engineering from Seoul National University, Seoul, South Korea, in 2010 and 2016, respectively.,In 2016, he was with the Inter-University Semiconductor Research Center, Seoul National University. From 2017 to 2019, he was a Post-Doctoral Researcher with the University of California at Berkeley, Berkeley, CA, USA. He is currently a Senior SerDes Engineer with the Ayar Labs, Santa Clara, CA, USA. His current research interests include integrated circuits for silicon photonics, high-speed I/O circuits and architectures, non-volatile memory systems, and agile hardware design methodology.,Dr. Bae was a recipient of the IEEE Circuits and Systems Society Outstan...

Publications

50

Citations

581

Publications by Year

20142024

Co-Authors:

Elad Alon
Erik Anderson
Shahab Ardalan
Krste Asanović
Jonathan Bachrach

Show All Co-Authors (119)

Author's Published Works

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Showing 1-25 of 50 results

Conferences (26)

Journals (24)

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Woorham Bae(48)
Deog-Kyoon Jeong(30)
Gyu-Seob Jeong(15)
Borivoje Nikolić(10)
Jaeduk Han(9)
Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA(10)
Department of Electrical and Computer Engineering, Seoul National University, Seoul, Korea(6)
Ayar Labs, Santa Clara, CA, USA(6)
Ayar Labs Inc, CA, USA(4)
Department of Electrical Engineering and Computer Science, Seoul National University, Seoul, Korea(2)
IEEE Journal of Solid-State Circuits(7)
IEEE Transactions on Circuits and Systems II: Express Briefs(4)
IEEE Transactions on Circuits and Systems I: Regular Papers(3)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems(3)
2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)(2)
IEEE(50)
Austin, TX, USA(2)
Honolulu, HI, USA(2)
Kyoto, Japan(2)
Lisbon, Portugal(2)
Montreal, QC, Canada(2)
Phase-locked Loop(23)
Power Consumption(16)
65-nm CMOS(14)
Data Rate(14)
Clock Frequency(13)

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A 256Gbps Microring-Based WDM Transceiver with Error-Free Wide Temperature Operation for Co-Packaged Optical I/O Chiplets

Pavan Bhargava;Daniel Jeong;Eric Jan;Derek Van Orden;Derek Kita;Hayk Gevorgyan;Sidney Buchbinder;Anatoly Khilo;Woorham Bae;Sung-Jin Kim;John Fini;Norman Chan;Chen Sun

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Year: 2024 | Conference Paper |

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We present a 256Gbps WDM transceiver macro for use in co-packaged AI scale-out interconnects. The macro adopts a $8\lambda\times 32\text{Gbps}$ configuration to achieve 256Gbps per fiber. The transceiver macro operates error-free across a dynamic temperature ramp of 50-110°C, has >4dB optical link margin with $4\text{dBm}/\lambda$ input laser power, and consumes 3.45pJ/b ($\text{TX}+\text{RX}$). A...Show More

A 256Gbps Microring-Based WDM Transceiver with Error-Free Wide Temperature Operation for Co-Packaged Optical I/O Chiplets

Pavan Bhargava;Daniel Jeong;Eric Jan;Derek Van Orden;Derek Kita;Hayk Gevorgyan;Sidney Buchbinder;Anatoly Khilo;Woorham Bae;Sung-Jin Kim;John Fini;Norman Chan;Chen Sun

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Year: 2024 | Conference Paper |

A High-Frequency and Low-Jitter DLL With Quadrature Error and Duty-Cycle Corrections Based on Asynchronous Sampling

Gijin Park;Dongjun Lee;Jaeduk Han;Woorham Bae

IEEE Solid-State Circuits Letters

Year: 2023 | Volume: 6 | Journal Article |

Cited by: Papers (5)

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This letter presents a quadrature error and duty-cycle correction circuit based on an asynchronous sampling technique. Sampling the multiphased clocks provides their phase and duty-cycle information, which are then utilized to compensate for the quadrature and duty-cycle errors. The intrinsic downconversion operation of the proposed sampling approach enhances the correction accuracy by mitigating ...Show More

A High-Frequency and Low-Jitter DLL With Quadrature Error and Duty-Cycle Corrections Based on Asynchronous Sampling

Gijin Park;Dongjun Lee;Jaeduk Han;Woorham Bae

IEEE Solid-State Circuits Letters

Year: 2023 | Volume: 6 | Journal Article |

Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures

Year: 2022 | Volume: 10 | Journal Article |

Cited by: Papers (7)

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A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most powerful indicator to compare and to normalize performance of different PLL designs. Simply, the conventional FOM is based on the jitter-power trade-off. With a few assumptions, theoretically, it provides a fair comparison. However, as the PLL design techniques have advanced, the assumptions have started brea...Show More

Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures

Year: 2022 | Volume: 10 | Journal Article |

In-Memory Hamming Error-Correcting Code in Memristor Crossbar

Woorham Bae;Jin-Woo Han;Kyung Jean Yoon

IEEE Transactions on Electron Devices

Year: 2022 | Volume: 69, Issue: 7 | Journal Article |

Cited by: Papers (3)

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This article proposes an in-memory Hamming error-correcting code (ECC) in the memristor crossbar array (CBA). Based on the unique ${I}{-}{V}$ characteristic of complementary resistive switching (CRS) memristor, this work discovers that a combination of three memristors behaves as a stateful EXCLUSIVE-OR (XOR) logic device. In addition, a two-step (build-up and fire) current-mode CBA driving sche...Show More

In-Memory Hamming Error-Correcting Code in Memristor Crossbar

Woorham Bae;Jin-Woo Han;Kyung Jean Yoon

IEEE Transactions on Electron Devices

Year: 2022 | Volume: 69, Issue: 7 | Journal Article |

An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET

Colin Schmidt;John Wright;Zhongkai Wang;Eric Chang;Albert Ou;Woorham Bae;Sean Huang;Vladimir Milovanović;Anita Flynn;Brian Richards;Krste Asanović;Elad Alon;Borivoje Nikolić

IEEE Journal of Solid-State Circuits

Year: 2022 | Volume: 57, Issue: 1 | Journal Article |

Cited by: Papers (12)

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This work presents a RISC-V system-on-chip (SoC) with eight application cores containing programmable-precision vector accelerators. The SoC is built by using a generator-based design methodology, which enables the integration of open-source and project-specific building blocks to develop differentiated functionality. The digital component generators use Chisel, the analog component generators use...Show More

An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET

Colin Schmidt;John Wright;Zhongkai Wang;Eric Chang;Albert Ou;Woorham Bae;Sean Huang;Vladimir Milovanović;Anita Flynn;Brian Richards;Krste Asanović;Elad Alon;Borivoje Nikolić

IEEE Journal of Solid-State Circuits

Year: 2022 | Volume: 57, Issue: 1 | Journal Article |

Monolithic Microring-based WDM Optical I/O for Heterogeneous Computing

Mark Wade;Daniel Jeong;Byungchae Kim;Mason Zhang;Woorham Bae;Chong Zhang;Pavan Bhargava;Derek Van Orden;Shahab Ardalan;Chandarasekaran Ramamurthy;Erik Anderson;Austin Katzin;Haiwei Lu;Sidney Buchbinder;Behrooz Beheshtian;Anatoly Khilo;Michael Rust;Chen Li;Forrest Sedgwick;John Fini;Roy Meade;Vladimir Stojanović;Chen Sun

2021 Symposium on VLSI Technology

Year: 2021 | Conference Paper |

Cited by: Papers (1)

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For the first time, we demonstrate an error-free, 128Gbps (8x16Gbps) optical transceiver using a microring-based wavelength-division multiplexed (WDM) architecture. The optical transceiver ran for 12 hours with zero errors, resulting in a measured bit-error rate of <1.45e-15 per optical lane. The total number of bits sent during this time was ~691 terabits per lane and ~5.5 petabits aggregate acro...Show More

Monolithic Microring-based WDM Optical I/O for Heterogeneous Computing

Mark Wade;Daniel Jeong;Byungchae Kim;Mason Zhang;Woorham Bae;Chong Zhang;Pavan Bhargava;Derek Van Orden;Shahab Ardalan;Chandarasekaran Ramamurthy;Erik Anderson;Austin Katzin;Haiwei Lu;Sidney Buchbinder;Behrooz Beheshtian;Anatoly Khilo;Michael Rust;Chen Li;Forrest Sedgwick;John Fini;Roy Meade;Vladimir Stojanović;Chen Sun

2021 Symposium on VLSI Technology

Year: 2021 | Conference Paper |

Monolithic Microring-based WDM Optical I/O for Heterogeneous Computing

Mark Wade;Daniel Jeong;Byungchae Kim;Mason Zhang;Woorham Bae;Chong Zhang;Pavan Bhargava;Derek Van Orden;Shahab Ardalan;Chandarasekaran Ramamurthy;Erik Anderson;Austin Katzin;Haiwei Lu;Sidney Buchbinder;Behrooz Beheshtian;Anatoly Khilo;Michael Rust;Chen Li;Forrest Sedgwick;John Fini;Roy Meade;Vladimir Stojanović;Chen Sun

2021 Symposium on VLSI Circuits

Year: 2021 | Conference Paper |

Cited by: Papers (6)

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For the first time, we demonstrate an error-free, 128Gbps (8x16Gbps) optical transceiver using a microring-based wavelength-division multiplexed (WDM) architecture. The optical transceiver ran for 12 hours with zero errors, resulting in a measured bit-error rate of <1.45e-15 per optical lane. The total number of bits sent during this time was ~691 terabits per lane and ~5.5 petabits aggregate acro...Show More

Monolithic Microring-based WDM Optical I/O for Heterogeneous Computing

Mark Wade;Daniel Jeong;Byungchae Kim;Mason Zhang;Woorham Bae;Chong Zhang;Pavan Bhargava;Derek Van Orden;Shahab Ardalan;Chandarasekaran Ramamurthy;Erik Anderson;Austin Katzin;Haiwei Lu;Sidney Buchbinder;Behrooz Beheshtian;Anatoly Khilo;Michael Rust;Chen Li;Forrest Sedgwick;John Fini;Roy Meade;Vladimir Stojanović;Chen Sun

2021 Symposium on VLSI Circuits

Year: 2021 | Conference Paper |

An Error-free 1 Tbps WDM Optical I/O Chiplet and Multi-wavelength Multi-port Laser

M. Wade;E. Anderson;S. Ardalan;W. Bae;B. Beheshtian;S. Buchbinder;K. Chang;P. Chao;H. Eachempatti;J. Frey;E. Jan;A. Katzin;A. Khilo;D. Kita;U. Krishnamoorthy;C. Li;H. Lu;F. Luna;C. Madden;L. Okada;M. Patel;C. Ramamurthy;M. Raval;R. Roucka;K. Robberson;M. Rust;D. Van Orden;R. Zeng;M. Zhang;V. Stojanovic;F. Sedgwick;R. Meade;N. Chan;J. Fini;B. Kim;S. Liu;C. Zhang;D. Jeong;P. Bhargava;M. Sysak;C. Sun

2021 Optical Fiber Communications Conference and Exhibition (OFC)

Year: 2021 | Conference Paper |

Cited by: Papers (4)

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We demonstrate 128 Gbps/port (8-λ×16 Gbps/λ) natively error-free transmission across eight optical ports using a 8-port, 8-λ/port WDM remote laser source and a pair of monolithically integrated CMOS optical I/O chiplets with 4.96-5.56 pJ/bit optical Tx+Rx chiplet energy efficiency.Show More

An Error-free 1 Tbps WDM Optical I/O Chiplet and Multi-wavelength Multi-port Laser

M. Wade;E. Anderson;S. Ardalan;W. Bae;B. Beheshtian;S. Buchbinder;K. Chang;P. Chao;H. Eachempatti;J. Frey;E. Jan;A. Katzin;A. Khilo;D. Kita;U. Krishnamoorthy;C. Li;H. Lu;F. Luna;C. Madden;L. Okada;M. Patel;C. Ramamurthy;M. Raval;R. Roucka;K. Robberson;M. Rust;D. Van Orden;R. Zeng;M. Zhang;V. Stojanovic;F. Sedgwick;R. Meade;N. Chan;J. Fini;B. Kim;S. Liu;C. Zhang;D. Jeong;P. Bhargava;M. Sysak;C. Sun

2021 Optical Fiber Communications Conference and Exhibition (OFC)

Year: 2021 | Conference Paper |

State-of-the-Art Circuit Techniques for Low-Jitter Phase-Locked Loops: Advanced Performance Benchmark FOM Based on an Extensive Survey

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

Year: 2021 | Conference Paper |

Cited by: Papers (5)

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A conventional figure-of-merit for a phase-locked loop (PLL) based on integrated RMS jitter and power consumption has been a strong indicator to compare and to normalize PLL performance over different designs. However, it has some limitations because any impact from reference clock is not reflected. As a result, it is not enough to evaluate state-of-the- art PLL designs such as injection-locked PL...Show More

State-of-the-Art Circuit Techniques for Low-Jitter Phase-Locked Loops: Advanced Performance Benchmark FOM Based on an Extensive Survey

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

Year: 2021 | Conference Paper |

4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET

Colin Schmidt;John Wright;Zhongkai Wang;Eric Chang;Albert Ou;Woorham Bae;Sean Huang;Anita Flynn;Brian Richards;Krste Asanović;Elad Alon;Borivoje Nikolić

2021 IEEE International Solid-State Circuits Conference (ISSCC)

Year: 2021 | Conference Paper |

Cited by: Papers (9)

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Modern workloads, such as deep neural networks (DNNs), increasingly rely on dense arithmetic compute patterns that are ill-suited for general-purpose processors, leading to a rise in domain-specific compute accelerators [1]. Many of these workloads can benefit from varying precision during computation, e.g. different precisions among layers and between training and inference for DNNs has been show...Show More

4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET

Colin Schmidt;John Wright;Zhongkai Wang;Eric Chang;Albert Ou;Woorham Bae;Sean Huang;Anita Flynn;Brian Richards;Krste Asanović;Elad Alon;Borivoje Nikolić

2021 IEEE International Solid-State Circuits Conference (ISSCC)

Year: 2021 | Volume: 64 | Conference Paper |

LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies

Jaeduk Han;Woorham Bae;Eric Chang;Zhongkai Wang;Borivoje Nikolić;Elad Alon

IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2021 | Volume: 68, Issue: 3 | Journal Article |

Cited by: Papers (23)

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LAYout with Gridded Objects (LAYGO), a Python-based layout-generation engine for enhancing the design productivity of custom circuit layouts in advanced CMOS processes, is presented and verified by implementing a time-interleaved SAR (TI-SAR) ADC instance in a 16 nm CMOS FinFET technology. LAYGO supports rapid generation by placing customized templates on process-specific placement grids, thereby ...Show More

LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies

Jaeduk Han;Woorham Bae;Eric Chang;Zhongkai Wang;Borivoje Nikolić;Elad Alon

IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2021 | Volume: 68, Issue: 3 | Journal Article |

TeraPHY: An O-Band WDM Electro-Optic Platform for Low Power, Terabit/s Optical I/O

Chen Sun;Daniel Jeong;Mason Zhang;Woorham Bae;Chong Zhang;Pavan Bhargava;Derek Van Orden;Shahab Ardalan;Chandarasekaran Ramamurthy;Erik Anderson;Austin Katzin;Haiwei Lu;Sidney Buchbinder;Behrooz Beheshtian;Anatoly Khilo;Michael Rust;Chen Li;Forrest Sedgwick;John Fini;Roy Meade;Vladimir Stojanović;Mark Wade

2020 IEEE Symposium on VLSI Technology

Year: 2020 | Conference Paper |

Cited by: Papers (26)

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We demonstrate an electro-optic platform enabling a direct optical I/O interface in an ASIC package. The 5.5×8.9mm2 chiplet uses the Advanced Interface Bus (AIB), a parallel digital interface, to communicate to a host ASIC and integrates high-speed digital/analog circuits, optical modulators, photodetectors, and waveguides. Transmitters and receivers demonstrate data-rates up to 25Gbps at 4.9pJ/bi...Show More

TeraPHY: An O-Band WDM Electro-Optic Platform for Low Power, Terabit/s Optical I/O

Chen Sun;Daniel Jeong;Mason Zhang;Woorham Bae;Chong Zhang;Pavan Bhargava;Derek Van Orden;Shahab Ardalan;Chandarasekaran Ramamurthy;Erik Anderson;Austin Katzin;Haiwei Lu;Sidney Buchbinder;Behrooz Beheshtian;Anatoly Khilo;Michael Rust;Chen Li;Forrest Sedgwick;John Fini;Roy Meade;Vladimir Stojanović;Mark Wade

2020 IEEE Symposium on VLSI Technology

Year: 2020 | Conference Paper |

Comprehensive Read Margin and BER Analysis of One Selector-One Memristor Crossbar Array Considering Thermal Noise of Memristor With Noise-Aware Device Model

Woorham Bae;Kyung Jean Yoon

IEEE Transactions on Nanotechnology

Year: 2020 | Volume: 19 | Journal Article |

Cited by: Papers (8)

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It can never be overemphasized the importance of understanding noise in electronics. However, it has not been deeply considered in memristor-based circuits and systems, while there have been tons of efforts to utilize the memristors to improve the present computing system. This article presents comprehensive read margin and bit-error-rate (BER) analyses, where the noise contributions from the memr...Show More

Comprehensive Read Margin and BER Analysis of One Selector-One Memristor Crossbar Array Considering Thermal Noise of Memristor With Noise-Aware Device Model

Woorham Bae;Kyung Jean Yoon

IEEE Transactions on Nanotechnology

Year: 2020 | Volume: 19 | Journal Article |

A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET

Jaeduk Han;Eric Chang;Stevo Bailey;Zhongkai Wang;Woorham Bae;Angie Wang;Nathan Narevsky;Amy Whitcombe;Pengpeng Lu;Borivoje Nikolić;Elad Alon

2019 IEEE Custom Integrated Circuits Conference (CICC)

Year: 2019 | Conference Paper |

Cited by: Papers (4)

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This paper presents a 7GS/s 8-bit time-interleaved SAR ADC instance produced from a generator-based design flow in a 16nm CMOS FinFET technology. Design techniques such as cross-coupled routing and clock delay modulation are utilized for compatibility with a FinFET process. The time-interleaved SAR ADC layout is automatically generated by placing templates and wires on a grid to abstract design ru...Show More

A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET

Jaeduk Han;Eric Chang;Stevo Bailey;Zhongkai Wang;Woorham Bae;Angie Wang;Nathan Narevsky;Amy Whitcombe;Pengpeng Lu;Borivoje Nikolić;Elad Alon

2019 IEEE Custom Integrated Circuits Conference (CICC)

Year: 2019 | Conference Paper |

A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance

Steven Bailey;Paul Rigge;Jaeduk Han;Richard Lin;Eric Y. Chang;Howard Mao;Zhongkai Wang;Chick Markley;Adam M. Izraelevitz;Angie Wang;Nathan Narevsky;Woorham Bae;Steve Shauck;Sergio Montano;Justin Norsworthy;Munir Razzaque;Wen Hau Ma;Akalu Lentiro;Matthew Doerflein;Darin Heckendorn;Jim McGrath;Franco DeSeta;Ronen Shoham;Mike Stellfox;Mark Snowden;Joseph Cole;Daniel R. Fuhrman;Brian Richards;Jonathan Bachrach;Elad Alon;Borivoje Nikolić

IEEE Journal of Solid-State Circuits

Year: 2019 | Volume: 54, Issue: 10 | Journal Article |

Cited by: Papers (15)

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This paper demonstrates a signal analysis systemon-chip (SoC) consisting of a general-purpose RISC-V core with vector extensions and a fixed-function signal-processing accelerator. Both the application core and the accelerators are design instances produced through an agile design-space exploration process by generators that allow for a wide range of parameter configurations. The signal processing...Show More

A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance

Steven Bailey;Paul Rigge;Jaeduk Han;Richard Lin;Eric Y. Chang;Howard Mao;Zhongkai Wang;Chick Markley;Adam M. Izraelevitz;Angie Wang;Nathan Narevsky;Woorham Bae;Steve Shauck;Sergio Montano;Justin Norsworthy;Munir Razzaque;Wen Hau Ma;Akalu Lentiro;Matthew Doerflein;Darin Heckendorn;Jim McGrath;Franco DeSeta;Ronen Shoham;Mike Stellfox;Mark Snowden;Joseph Cole;Daniel R. Fuhrman;Brian Richards;Jonathan Bachrach;Elad Alon;Borivoje Nikolić

IEEE Journal of Solid-State Circuits

Year: 2019 | Volume: 54, Issue: 10 | Journal Article |

A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET

Angie Wang;Woorham Bae;Jaeduk Han;Stevo Bailey;Orhan Ocal;Paul Rigge;Zhongkai Wang;Kannan Ramchandran;Elad Alon;Borivoje Nikolić

IEEE Journal of Solid-State Circuits

Year: 2019 | Volume: 54, Issue: 7 | Journal Article |

Cited by: Papers (6)

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A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis system-on-chip (SoC), integrating a subsampling analog-to-digital converter (ADC) frontend with a digital reconstruction backend and implementing a 21 600-point sparse Fourier transform based on the fast Fourier aliasing-based sparse transform (FFAST) algorithm has been co-designed by using the Constructing Hardware in a Scala Embedded Lan...Show More

A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET

Angie Wang;Woorham Bae;Jaeduk Han;Stevo Bailey;Orhan Ocal;Paul Rigge;Zhongkai Wang;Kannan Ramchandran;Elad Alon;Borivoje Nikolić

IEEE Journal of Solid-State Circuits

Year: 2019 | Volume: 54, Issue: 7 | Journal Article |

Reference Spur Reduction Techniques for a Phase-Locked Loop

Han-Gon Ko;Woorham Bae;Gyu-Seob Jeong;Deog-Kyoon Jeong

Year: 2019 | Volume: 7 | Journal Article |

Cited by: Papers (13)

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This paper presents the reference spur reduction techniques for an analog phase-locked loop (PLL). A simple leakage compensation loop is proposed, which cancels the leakage current of the PLL loop filter with a negligible power overhead. This leakage compensation loop senses the leakage current of the loop filter from the up and down pulse widths in the steady state and compensates for the charge ...Show More

Reference Spur Reduction Techniques for a Phase-Locked Loop

Han-Gon Ko;Woorham Bae;Gyu-Seob Jeong;Deog-Kyoon Jeong

Year: 2019 | Volume: 7 | Journal Article |

A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET

Stevo Bailey;Jaeduk Han;Paul Rigge;Richard Lin;Eric Chang;Howard Mao;Zhongkai Wang;Chick Markley;Adam Izraelevitz;Angie Wang;Nathan Narevsky;Woorham Bae;Steve Shauck;Sergio Montano;Justin Norsworthy;Munir Razzaque;Wen Hau Ma;Akalu Lentiro;Matthew Doerflein;Darin Heckendorn;Jim McGrath;Franco DeSeta;Ronen Shoham;Mike Stellfox;Mark Snowden;Joseph Cole;Dan Fuhrman;Brian Richards;Jonathan Bachrach;Elad Alon;Borivoje Nikolić

2018 IEEE Asian Solid-State Circuits Conference (A-SSCC)

Year: 2018 | Conference Paper |

Cited by: Papers (4)

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This paper demonstrates a signal analysis SoC consisting of a general-purpose RISC-V core with vector extensions and a fixed-function signal-processing accelerator. Both the core and the accelerators are instances produced by novel generators that allow for a wide range of parameter configurations and rapid design space exploration. The signal processing chain consists of generated instances of a ...Show More

A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET

Stevo Bailey;Jaeduk Han;Paul Rigge;Richard Lin;Eric Chang;Howard Mao;Zhongkai Wang;Chick Markley;Adam Izraelevitz;Angie Wang;Nathan Narevsky;Woorham Bae;Steve Shauck;Sergio Montano;Justin Norsworthy;Munir Razzaque;Wen Hau Ma;Akalu Lentiro;Matthew Doerflein;Darin Heckendorn;Jim McGrath;Franco DeSeta;Ronen Shoham;Mike Stellfox;Mark Snowden;Joseph Cole;Dan Fuhrman;Brian Richards;Jonathan Bachrach;Elad Alon;Borivoje Nikolić

2018 IEEE Asian Solid-State Circuits Conference (A-SSCC)

Year: 2018 | Conference Paper |

A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET

Angie Wang;Woorham Bae;Jaeduk Han;Stevo Bailey;Paul Rigge;Orhan Ocal;Zhongkai Wang;Kannan Ramchandran;Elad Alon;Borivoje Nikolić

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)

Year: 2018 | Conference Paper |

Cited by: Papers (4)

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A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis SoC, integrating a subsampling ADC frontend with a digital reconstruction backend and implementing a 21,600-point FFAST sparse FFT [1] has been generated using the Chisel [2] and BAG [3] frameworks in 16-nm CMOS. Three sets of 25×, 27×, and 32×subsampling SAR ADCs acquire signal with ~5.4-6.3 ENOB/slice. The digital backend consists of mix...Show More

A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET

Angie Wang;Woorham Bae;Jaeduk Han;Stevo Bailey;Paul Rigge;Orhan Ocal;Zhongkai Wang;Kannan Ramchandran;Elad Alon;Borivoje Nikolić

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)

Year: 2018 | Conference Paper |

A Variation-Tolerant, Sneak-Current-Compensated Readout Scheme for Cross-Point Memory Based on Two-Port Sensing Technique

Woorham Bae;Kyung Jean Yoon;Taeksang Song;Borivoje Nikolić

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2018 | Volume: 65, Issue: 12 | Journal Article |

Cited by: Papers (8)

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A variation-tolerant and sneak-current-free readout technique for cross-point non-volatile memory is presented. The proposed readout circuit has a sneak current compensation port, which collects sneak current information from multiple unselected cells, and efficiently cancels it out without delay and area overhead. In addition, this scheme averages out the random mismatches in the unselected cells...Show More

A Variation-Tolerant, Sneak-Current-Compensated Readout Scheme for Cross-Point Memory Based on Two-Port Sensing Technique

Woorham Bae;Kyung Jean Yoon;Taeksang Song;Borivoje Nikolić

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2018 | Volume: 65, Issue: 12 | Journal Article |

A 6.7–11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS

Kwanseo Park;Woorham Bae;Jinhyung Lee;Jeongho Hwang;Deog-Kyoon Jeong

IEEE Journal of Solid-State Circuits

Year: 2018 | Volume: 53, Issue: 10 | Journal Article |

Cited by: Papers (38)

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A single-loop referenceless clock and data recovery (CDR) with a compact frequency acquisition scheme is presented. A bang-bang phase-frequency detector (BBPFD) is proposed that tracks the frequency difference by detecting the drift direction of the non-return to zero bit stream with respect to the multi-phase clock and generates UP/DN output signals accordingly. When frequency locked, the BBPFD i...Show More

A 6.7–11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS

Kwanseo Park;Woorham Bae;Jinhyung Lee;Jeongho Hwang;Deog-Kyoon Jeong

IEEE Journal of Solid-State Circuits

Year: 2018 | Volume: 53, Issue: 10 | Journal Article |

BAG2: A process-portable framework for generator-based AMS circuit design

Eric Chang;Jaeduk Han;Woorham Bae;Zhongkai Wang;Nathan Narevsky;Borivoje NikoliC;Elad Alon

2018 IEEE Custom Integrated Circuits Conference (CICC)

Year: 2018 | Conference Paper |

Cited by: Papers (92)

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We present BAG2, a framework for the development of process-portable Analog and Mixed Signal (AMS) circuit generators. Such generators are parametrized design procedures that produce schematics, layouts, and verification testbenches for a circuit given input specifications. This paper expands on previous work by introducing a universal AMS circuit verification framework into BAG2, as well as two n...Show More

BAG2: A process-portable framework for generator-based AMS circuit design

Eric Chang;Jaeduk Han;Woorham Bae;Zhongkai Wang;Nathan Narevsky;Borivoje NikoliC;Elad Alon

2018 IEEE Custom Integrated Circuits Conference (CICC)

Year: 2018 | Conference Paper |

A 2.5–5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection

Sung-Yong Cho;Sungwoo Kim;Min-Seong Choo;Han-Gon Ko;Jinhyung Lee;Woorham Bae;Deog-Kyoon Jeong

IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2018 | Volume: 65, Issue: 9 | Journal Article |

Cited by: Papers (21)

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A 2.5-5.6 GHz low-phase-noise subharmonically injection-locked sub-sampling all-digital phase-locked loop with a dual-edge complementary switched injection technique is presented. While previously reported injection-locked phase-locked loops (ILPLLs) require additional circuitry for resolving a phase alignment mismatch between the PLL loop and injection path, the presented ILPLL exhibits a simplif...Show More

A 2.5–5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection

Sung-Yong Cho;Sungwoo Kim;Min-Seong Choo;Han-Gon Ko;Jinhyung Lee;Woorham Bae;Deog-Kyoon Jeong

IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2018 | Volume: 65, Issue: 9 | Journal Article |

A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards

Woorham Bae;Haram Ju;Kwanseo Park;Jaeduk Han;Deog-Kyoon Jeong

IEEE Transactions on Industrial Electronics

Year: 2018 | Volume: 65, Issue: 7 | Journal Article |

Cited by: Papers (10)

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Supporting a wide operating range for industrial-standard backward-compatible transmitters often results in energy inefficiency. This paper describes an energy-efficient voltage-mode-serializing transmitter with an operating range of up to 32 Gb/s. The proposed transmitter uses a programmable internal supply to set the voltage level for various data rates optimally, thus improving overall energy e...Show More

A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards

Woorham Bae;Haram Ju;Kwanseo Park;Jaeduk Han;Deog-Kyoon Jeong

IEEE Transactions on Industrial Electronics

Year: 2018 | Volume: 65, Issue: 7 | Journal Article |

A 32 Gb/s, 201 mW, MZM/EAM Cascode Push–Pull CML Driver in 65 nm CMOS

Jeongho Hwang;Gyu-Seob Jeong;Woorham Bae;Jun-Eun Park;Chang Soo Yoon;Jung Min Yoon;Jiho Joo;Gyungock Kim;Deog-Kyoon Jeong

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2018 | Volume: 65, Issue: 4 | Journal Article |

Cited by: Papers (15)

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This brief presents a 32 Gb/s driver for a Mach-Zehnder modulator (MZM) and an electro-absorption modulator (EAM). A push-pull current-mode logic driver is chosen to achieve a better power efficiency and a large voltage swing. A double cascode with thin oxide transistors is employed to mitigate the over-voltage stress associated with a large output voltage swing. At the same time, shunt-peaking in...Show More

A 32 Gb/s, 201 mW, MZM/EAM Cascode Push–Pull CML Driver in 65 nm CMOS

Jeongho Hwang;Gyu-Seob Jeong;Woorham Bae;Jun-Eun Park;Chang Soo Yoon;Jung Min Yoon;Jiho Joo;Gyungock Kim;Deog-Kyoon Jeong

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2018 | Volume: 65, Issue: 4 | Journal Article |

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