Generation and Implementation of Random Number Architecture using Difference Expansion for Digital Circuits

Unified logic and very large-scale integration (VLSI) circuitry have been created to generate random numbers from various distributions such as uniform, exponential, and Gauss distributions. An arithmetic iteration notion is used to implement several architectural levels in the proposed system. Fast speed, low power consumption, and great output accuracy make this random number generator ideal for communications systems and other models that need multi-distribution random numbers. The difference expansion approach and linear feedback shift register (LFSR) bit switching are recommended to generate random numbers. Besides this, the randomization is unpredictably random. Predictable binary sequences have been a major drawback of earlier randomization approaches. Differential characteristics construct the sequence and keep things simple in this technique. It also aims to simplify the circuit and use less energy. Power, delay, and a lookup table are used to make performance comparisons. The proposed architecture was tested and evaluated using Xilinx. Simulation results demonstrate that the proposed model outperforms standard random generators using Slices, Area, and Look Up Tables. According to the research findings, the proposed Difference Expansion-based Random Generation (DERG) has reduced latency and consumes less power.