Implementation of Spurious Power Suppression based Radix-4 Booth Multiplier using Parallel Prefix Adders

In VLSI, for performing multiplication, we use a*b. We use the booth multiplication mechanism rather than the standard conventional method to improve the speed since it generally requires lower power, area and reduces delay. Some bits overlap with each other during the multiplication process in the convectional multiplication method (whereas booth multipliers consist of shifting process), making the system more complex and decreasing output efficiency. To overcome this, SPST is implemented such that unwanted transactions are neglected and also eliminate the overlapping bits. This affects the carry changes and data generation parts and even reduces the unwanted power flow in adders. It uses Radix 4 multiplier, which requires addition processors. In the previous multipliers usage of Ripple carry adder, Carry save adder, carry ahead adder, which are the basic types of serial adders where they utilize serial adding mechanism where the data is processed bit by bit that make the system more complicated. To reduce these problems, we are using parallel prefix adders that work in a higher speed manner, which uses carry propagation and carry generation internally to perform additional operations and improve speed. So, this project is implemented in VLSI prototype with respect to Xilinx ISE software and Verilog programming language.