DPU: DAG Processing Unit for Irregular Graphs With Precision-Scalable Posit Arithmetic in 28 nm

Computation in several real-world applications such as probabilistic machine learning, sparse linear algebra, and robotic navigation can be modeled as irregular directed acyclic graphs (DAGs). The irregular data dependencies in DAGs pose challenges to parallel execution on general-purpose CPUs and GPUs, resulting in severe under-utilization of the hardware. This article proposes DAG Processing Unit (DPU), a specialized processor designed for the efficient execution of irregular DAGs. The DPU is equipped with parallel compute units (CUs) that execute different subgraphs of a DAG independently. The CUs can synchronize within a cycle using a hardware-supported synchronization primitive and communicate via an efficient interconnect to a global banked scratchpad. Furthermore, a precision-scalable positTrademarked. arithmetic unit is developed to enable application-dependent precision. The DPU is taped out in 28-nm CMOS, achieving a speedup of 5.1 $\times $ and 20.6 $\times $ over state-of-the-art CPU and GPU implementations on DAGs of sparse linear algebra and probabilistic machine learning workloads. This performance is achieved while operating at a power budget of 0.23 W, as opposed to 55 and 98 W of the CPU and GPU, resulting in a peak efficiency of 538 GOPS/W with DPU, which is 1350 $\times $ and 9000 $\times $ higher than the CPU and GPU, respectively. Thus, with specialized architecture, DPU enables low-power execution of irregular DAG workloads.