Abstract:
A wireline receiver consisting of a linear equalizer, a decision-feedback equalizer (DFE), a clock and data recovery (CDR) circuit, and a demultiplexer (DMUX) employs new...Show MoreMetadata
Abstract:
A wireline receiver consisting of a linear equalizer, a decision-feedback equalizer (DFE), a clock and data recovery (CDR) circuit, and a demultiplexer (DMUX) employs new circuit and architecture techniques that afford substantial power savings. Realized in 28-nm technology, the 56-Gb/s receiver has a bit error rate (BER) of less than 10 ^{-12} for a channel loss of 25 dB at 28 GHz.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 57, Issue: 1, January 2022)