Abstract:
This paper proposes a parallel-to-series combined Doherty power amplifier (PA) in 28-nm bulk CMOS technology that improves the operation bandwidth and minimizes the die a...Show MoreMetadata
Abstract:
This paper proposes a parallel-to-series combined Doherty power amplifier (PA) in 28-nm bulk CMOS technology that improves the operation bandwidth and minimizes the die area for the Doherty output network. The two-stage differential Doherty PA shows a saturated output power (POUT) of >18.8dBm and a peak power-added efficiency (PAE) of >30% at 27GHz CW. Under the 5G NR 64QAM OFDM signal (\text{PAPR} > 10\text{dB}), the PA achieves a linear POUT of 12.4dBm and an average PAE of 20.2% at an EVM of −25dB. Over the frequency range of 24.5-29.5GHz, the PA exhibits a linear POUT of >11.2dBm and a PAE of >14.5% (\text{DE} > 20.8\%). This compact PA IC occupies 640\times 250\mu\mathrm{m}^{2} (core).
Date of Conference: 07-09 June 2021
Date Added to IEEE Xplore: 28 July 2021
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