Ring Oscillator with Improved Design

This paper presents a design of stacked inverter-based ring oscillator. The proposed work includes an approach to minimize variations across all the Process Voltage Temperature (PVT) conditions with a power consumption of 27.36 μ W at 25° C. The design consists of trim bits to decrease the frequency variations across process corners. The voltage biasing circuit facilitates minimum variations across temperature. The simulation results using Cadence Virtuoso for gpdk90 CMOS technology shows a good agreement with analysis results. The design works at 1MHz frequency for a supply voltage of 1.8V. The stability checked across a temperature of -40 to 125°C is +/-14% variation across PVT.