Irregular Sampling of Regular Waveform Based Random Number Generator Exploiting Two Simultaneous Metastable Events of Tetrahedral Oscillators

An irregular sampling of regular waveform based random number generator(RNG) is proposed. The entropy source is constructed by using modified tetrahedral ring oscillators which exploits two metastable events in the circuit by switching the stable and unstable loops with a clock signal with help of additional inverters which can be turned on and off. The obtained circuit has higher entropy than the classical tetrahedral ring oscillator. The design is implemented using VHDL on Xilinx Zedboard Zynq Development Board as a proof of concept. The regular clock is adjusted to have close 50% duty cycle and a frequency at least 200 times of the irregular clock which has a center frequency of 70MHz and the rings are placed around the XOR gate in a circle to achieve higher entropy. The regular clock is sampled with the irregular clock and the sampled data is collected by using a UART module and TTL cable. The collected data sets are tested with National Institute of Standard and Technology (NIST) test suite to prove the randomness and they passed all the tests with success. The RNG has a bit rate of 273kb/s and it is implemented with 5 oscillators. The proposed architecture has a 2.73 times speed improvement and uses half the ring number to generate random number sequence without any post processing.