Abstract:
The transistors used to construct Integrated Circuits (ICs) continue to shrink. While this shrinkage improves performance and density, it also reduces trust: the price to...Show MoreMetadata
Abstract:
The transistors used to construct Integrated Circuits (ICs) continue to shrink. While this shrinkage improves performance and density, it also reduces trust: the price to build leading-edge fabrication facilities has skyrocketed, forcing even nation states to outsource the fabrication of high-performance ICs. Outsourcing fabrication presents a security threat because the black-box nature of a fabricated IC makes comprehensive inspection infeasible. Since prior work shows the feasibility of fabrication-time attackers' evasion of existing post-fabrication defenses, IC designers must be able to protect their physical designs before handing them off to an untrusted foundry. To this end, recent work suggests methods to harden IC layouts against attack. Unfortunately, no tool exists to assess the effectiveness of the proposed defenses, thus leaving defensive gaps.This paper presents an extensible IC layout security analysis tool called IC Attack Surface (ICAS) that quantifies defensive coverage. For researchers, ICAS identifies gaps for future defenses to target, and enables the quantitative comparison of existing and future defenses. For practitioners, ICAS enables the exploration of the impact of design decisions on an IC's resilience to fabrication-time attack. ICAS takes a set of metrics that encode the challenge of inserting a hardware Trojan into an IC layout, a set of attacks that the defender cares about, and a completed IC layout and reports the number of ways an attacker can add each attack to the design. While the ideal score is zero, practically, we find that lower scores correlate with increased attacker effort.To demonstrate ICAS' ability to reveal defensive gaps, we analyze over 60 layouts of three real-world hardware designs (a processor, AES and DSP accelerators), protected with existing defenses. We evaluate the effectiveness of each circuit-defense combination against three representative attacks from the literature. Results show that some defenses are ...
Published in: 2020 IEEE Symposium on Security and Privacy (SP)
Date of Conference: 18-21 May 2020
Date Added to IEEE Xplore: 30 July 2020
ISBN Information:
ISSN Information:
Keywords assist with retrieval of results and provide a means to discovering other relevant content. Learn more.
- IEEE Keywords
- Index Terms
- Extensive Framework ,
- Set Of Metrics ,
- Physical Design ,
- Physical Layout ,
- Attack Surface ,
- Integrated Circuit Design ,
- Set Of Attacks ,
- Behavioral Level ,
- Processing Technology ,
- Open Space ,
- Circuit Design ,
- Manhattan Distance ,
- Open Regions ,
- Open Sites ,
- Dense Core ,
- Device Layer ,
- Integration Points ,
- Circuit Components ,
- Clock Frequency ,
- Commercial Tools ,
- Route Distance ,
- Placement Sites ,
- Entire Design ,
- Space Metric ,
- Manual Identification ,
- Threat Model ,
- Additional Gate ,
- Time Constraints ,
- Contiguous Regions ,
- Increased Resource Utilization
Keywords assist with retrieval of results and provide a means to discovering other relevant content. Learn more.
- IEEE Keywords
- Index Terms
- Extensive Framework ,
- Set Of Metrics ,
- Physical Design ,
- Physical Layout ,
- Attack Surface ,
- Integrated Circuit Design ,
- Set Of Attacks ,
- Behavioral Level ,
- Processing Technology ,
- Open Space ,
- Circuit Design ,
- Manhattan Distance ,
- Open Regions ,
- Open Sites ,
- Dense Core ,
- Device Layer ,
- Integration Points ,
- Circuit Components ,
- Clock Frequency ,
- Commercial Tools ,
- Route Distance ,
- Placement Sites ,
- Entire Design ,
- Space Metric ,
- Manual Identification ,
- Threat Model ,
- Additional Gate ,
- Time Constraints ,
- Contiguous Regions ,
- Increased Resource Utilization