Hot Carrier Degradation in Cryo-CMOS

28nm Gate First High-K Metal Gate (GF-HKMG) technology is analyzed for Hot-Carrier Degradation (HCD) under varying gate/drain (V
_G
/V
_D
) bias and temperature (T: 300K to 77K). A compact model is used to partition measured threshold voltage shift (ΔV
_T
) into interface trap generation due to pure HCD (ΔV
_IT-HC
), Bias Temperature Instability (BTI, ΔV
_IT-BT
), and electron/hole trapping (ΔV
_ET
/ΔV
_HT
) subcomponents. The relative importance of the subcomponents is analyzed for varying T. Although pure HCD dominates under Cryo-CMOS operation, the T dependence is shown to be different for Si NMOS and SiGe PMOS FETs. Finally, the impact on the circuit (RO: Ring Oscillator) operation is analyzed.