Abstract:
This paper presents an ultra-low power digitally-assisted analog ring phase-locked loop (PLL) with a tunable switched capacitor loop filter. The PLL achieves a power effi...Show MoreMetadata
Abstract:
This paper presents an ultra-low power digitally-assisted analog ring phase-locked loop (PLL) with a tunable switched capacitor loop filter. The PLL achieves a power efficiency of 0.213mW/GHz and FoM of -234.4dB at. 08V supply with only 200ns lock time at 100MHz reference clock. All the components are using a single supply voltage and it can operate from 0.5V to 0.9V supply with a wide output clock frequency range from 0.2GHz to 5GHz. At 0.5V supply, it can support 1.6GHz operation with very high power efficiency of 0.08m W/GHz. It can also support a wide reference clock frequency range from 20MHz to 200MHz. This low power design is suitable for System-on-Chip (SoC) and Internet-of- Things (IoT) processors.
Published in: 2020 IEEE Custom Integrated Circuits Conference (CICC)
Date of Conference: 22-25 March 2020
Date Added to IEEE Xplore: 23 April 2020
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