A High Phase Accuracy Multiphase DLL with Optimized VCDL Structure

In this paper, a 4-phase delay-locked loop (DLL) with high phase accuracy, low power consumption and small area is realized for time-to-digital converter (TDC). The proposed DLL adopts a new voltage-controlled delay line (VCDL) structure, which reduces the output phase error down to 2.32%. A simple digital auxiliary pulse width regulator is used to adjust the width of output pulse for further reduction of the duty cycle error. Designed with 0.18 μm CMOS process, the DLL with 4-phase outputs occupies an active area of 102 μm × 100 μm. With a supply voltage of 1.8 V, the power and peak-to-peak jitter of this proposed DLL is 2.27 mW and 12.9 ps, respectively.