A New Approximate Multiplier Design for Digital Signal Processing | IEEE Conference Publication | IEEE Xplore

A New Approximate Multiplier Design for Digital Signal Processing


Abstract:

In this paper, a new approximate multiplier is proposed, which can decrease the multiplication complexity with the improved area and power performance by using OR and AND...Show More

Abstract:

In this paper, a new approximate multiplier is proposed, which can decrease the multiplication complexity with the improved area and power performance by using OR and AND gates. To evaluate the efficiency of the proposed approximate multiplier, design parameters are compared with exact multiplier and recently proposed approximate designs. Experiment results reveal that the power consumption of the proposed approximate multiplier is only 32% of that in the exact multiplier. The proposed approximate multipliers are further evaluated in image sharpening and edge detection applications. The peak signal to noise ratio (PSNR) and structural similarity (SSIM) of our proposed approximate multipliers show that it can be used in image processing.
Date of Conference: 29 October 2019 - 01 November 2019
Date Added to IEEE Xplore: 06 February 2020
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Conference Location: Chongqing, China

References

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