Abstract:
A new carry generation scheme for carry out bit of a 4-bit carry look-ahead (CLA) adder is presented. To analyze performance, proposed design for carry-out bit was implem...Show MoreMetadata
Abstract:
A new carry generation scheme for carry out bit of a 4-bit carry look-ahead (CLA) adder is presented. To analyze performance, proposed design for carry-out bit was implemented and verified in Cadence Virtuoso environment in 90nm technology. Performance parameters were compared with the conventional design of carry-out bit of 4-bit CLA adder. The proposed design achieved 19.69% improvement in propagation delay over the conventional CLA design. Due to low transistor count and low dynamic power dissipation, an improvement of 75.973% was achieved in average power consumption over the conventional carry-out bit of CLA design. As a result, the obtained improvement in PDP was 79.003%. Due to enhancements in performance parameters and reduced transistor count, the proposed CLA carry-out bit is expected to have extensive impact on overall adder performance.
Published in: 2019 10th International Conference on Computing, Communication and Networking Technologies (ICCCNT)
Date of Conference: 06-08 July 2019
Date Added to IEEE Xplore: 30 December 2019
ISBN Information: