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High Speed and Ultra Low Power Design of Carry-Out Bit of 4-Bit Carry Look-Ahead Adder | IEEE Conference Publication | IEEE Xplore

High Speed and Ultra Low Power Design of Carry-Out Bit of 4-Bit Carry Look-Ahead Adder


Abstract:

A new carry generation scheme for carry out bit of a 4-bit carry look-ahead (CLA) adder is presented. To analyze performance, proposed design for carry-out bit was implem...Show More

Abstract:

A new carry generation scheme for carry out bit of a 4-bit carry look-ahead (CLA) adder is presented. To analyze performance, proposed design for carry-out bit was implemented and verified in Cadence Virtuoso environment in 90nm technology. Performance parameters were compared with the conventional design of carry-out bit of 4-bit CLA adder. The proposed design achieved 19.69% improvement in propagation delay over the conventional CLA design. Due to low transistor count and low dynamic power dissipation, an improvement of 75.973% was achieved in average power consumption over the conventional carry-out bit of CLA design. As a result, the obtained improvement in PDP was 79.003%. Due to enhancements in performance parameters and reduced transistor count, the proposed CLA carry-out bit is expected to have extensive impact on overall adder performance.
Date of Conference: 06-08 July 2019
Date Added to IEEE Xplore: 30 December 2019
ISBN Information:
Conference Location: Kanpur, India

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