Reconfigurable Hybrid Cache Hierarchy in 3D Chip-Multi Processors Based on a Convex optimization Method

To overcome the challenges in Chip-Multi Processor (CMP) design as memory static power, memory wall, and limited memory bandwidth, by using hybrid cache technologies such as SRAM, DRAM, and STT-RAM. Besides that, many characteristics are extracted using these technologies like low leakage power, high-density storage, and non-volatility. In this paper, we provide an interesting approach for a reconfigurable hybrid cache architecture, in which STT-RAM banks are arranged in the last cache level with SRAM banks. Furthermore, the reconfiguration mechanism dynamically adapts the cache space based on the estimated optimal bandwidth demands of different applications. We execute experiments on a 16-core CMP which shows that the proposed design improves the power consumption higher than SRAM cache only and non-reconfigurable hybrid memory under multi-programmed and multithreaded applications.