Power-Management based on Reconfigurable Last-Cache level on Non-volatile Memories in Chip-Multi processors

With technology scaling and increasing parallelism levels of new embedded applications, multi-cores in chip-multiprocessors (CMP) has been increased. In this context, power consumption acts a critical issue concern in future CMPs with restricted of battery lifetime. For future CMPs architecting, 3D stacking of Last Level Cache (LLC) has been recently introduced as a new methodology to combat the performance challenges of 2D integration. However, the 3D design of LLCs incurs more leakage power utilization compared to conventional cache architectures in 2Ds due to dense integration. We present in this work a power-efficient reconfigurable hybrid last level cache architecture for future CMPs. The proposed hybrid architecture SRAM memory is incorporated with STT-RAM technology by using the characteristics for both new and traditional technologies. The experimental results show that the designed method minimizes power consumption under multi-programmed and multithreaded applications.

I. Introduction

In recent years, to address the requirement of new data-centric applications for larger memories and to break the memory wall problem, besides that, Last Level Cache (LLC) size is increased dramatically in the memory hierarchy. However, the increasing power consumption leads to raising the cost and then an increase of chip temperature. Increasing chip temperature and creating hot spots leads to reliability problems in the chip and reducing chip lifetime. In this regard, some architectures and techniques have been proposed for power management to reduce the dark area in multi/many core systems [1].