Abstract:
On-chip links significantly contribute to the consumption of systems on chip (SoCs), especially in highly-parallel architectures. Such architectures are widely used for s...Show MoreMetadata
Abstract:
On-chip links significantly contribute to the consumption of systems on chip (SoCs), especially in highly-parallel architectures. Such architectures are widely used for several applications that are inherently error-resilient (e.g., vision, machine learning), in which the energy-quality tradeoff can be exploited to achieve significant reduction in energy. This paper proposes the use of sub-word ranking and non-uniform swing to allow graceful energy-quality tradeoff in intra-chip communication links. The proposed techniques are demonstrated in a 28nm testchip that achieves up to 4.5X energy saving over conventional full-quality links, and up to 2.2X over approximate links at iso-quality. Conventional operation with no quality degradation is also allowed for data packets that require full quality.
Published in: 2019 IEEE Custom Integrated Circuits Conference (CICC)
Date of Conference: 14-17 April 2019
Date Added to IEEE Xplore: 01 August 2019
ISBN Information: