Dark Wires and the Opportunities for Reconfigurable Logic

Power has become a fundamental limit to silicon performance. Most research has focused on reducing transistor switching to constrain power (dark silicon.) Specialized accelerators have been proposed since they implement functionality with fewer transistor switches than general purpose cores. Increasing efficiency requirements lead to more specialization and, therefore, more accelerators that potentially leads to longer distances to get to all the accelerators. Communication, however, consumes energy, and therefore needs to be minimized as well (dark wires.) This paper examines the balance between compute and communication specialization in the context of hard logic (e.g., ASIC) that is highly efficient but static versus soft logic (e.g., FPGA) that is less efficient but allows computation to be moved to reduce communication distances. Our experimental results show using soft accelerators consumes 0.6×-2.1× total power compared to using hard accelerators when communication costs are taken into account.