Abstract:
A test structure suite to measure circuit delays, power, and operating margins of single flux quantum (SFQ) circuits and to derive key parameters directly from dc testabl...Show MoreMetadata
Abstract:
A test structure suite to measure circuit delays, power, and operating margins of single flux quantum (SFQ) circuits and to derive key parameters directly from dc testable high-speed circuits is described. This suite comprises a set of ring oscillators and a time-differential experiment as well as isolated circuit components. Measured data are compared to the results obtained from circuit simulations conducted in a design environment used for more complex chip designs. This approach, which enables tracking of process technology and validation of device and circuit models in a self-consistent manner, is inspired by a similar methodology for silicon technology deployed successfully by IBM and its alliance partners.
Published in: IEEE Transactions on Applied Superconductivity ( Volume: 29, Issue: 5, August 2019)
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- IEEE Keywords
- Index Terms
- Single Flux Quantum ,
- Circuit Model ,
- Device Model ,
- Circuit Simulation ,
- Flux Quantum ,
- Upper Limit ,
- Current Source ,
- Test Setup ,
- I-V Curves ,
- Lower Margin ,
- Device Parameters ,
- Critical Current ,
- Complex Circuits ,
- Bias Current ,
- Layout Design ,
- Datapath ,
- Shunt Resistance ,
- Technology Node ,
- Path Delay ,
- Physical Layout ,
- Josephson Junctions ,
- Design Style ,
- Manufacturing Line ,
- Parasitic Inductance ,
- IC Values ,
- Circuit Design ,
- Nominal Value ,
- Magnetic Field
- Author Keywords
Keywords assist with retrieval of results and provide a means to discovering other relevant content. Learn more.
- IEEE Keywords
- Index Terms
- Single Flux Quantum ,
- Circuit Model ,
- Device Model ,
- Circuit Simulation ,
- Flux Quantum ,
- Upper Limit ,
- Current Source ,
- Test Setup ,
- I-V Curves ,
- Lower Margin ,
- Device Parameters ,
- Critical Current ,
- Complex Circuits ,
- Bias Current ,
- Layout Design ,
- Datapath ,
- Shunt Resistance ,
- Technology Node ,
- Path Delay ,
- Physical Layout ,
- Josephson Junctions ,
- Design Style ,
- Manufacturing Line ,
- Parasitic Inductance ,
- IC Values ,
- Circuit Design ,
- Nominal Value ,
- Magnetic Field
- Author Keywords