Abstract:
A power amplifier (PA) with peak power-added efficiency (PAE) above 45% at output power of 19dBm implemented with pMOS in a 45nm SOI technology is reported. The power amp...Show MoreMetadata
Abstract:
A power amplifier (PA) with peak power-added efficiency (PAE) above 45% at output power of 19dBm implemented with pMOS in a 45nm SOI technology is reported. The power amplifier operates over a 25 to 31GHz frequency range with output power within 1dB of its peak value. The PA employs two stacked FETs, each with gate width 306um, and uses an accelerator capacitor to increase gain and efficiency. pMOSbased PAs are of interest because of their potential for higher immunity to hot-carrier injection than their nMOS counterparts. To the authors best knowledge, the PA provides the highest reported PAE for 28GHz applications of any pMOS circuit, and has efficiency comparable to the best reported for nMOS, SiGe HBT and GaAs pHEMT circuits. Amplifier design considerations for efficiency enhancement are discussed.
Date of Conference: 05-08 August 2018
Date Added to IEEE Xplore: 24 January 2019
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Department of Electrical and Computer Engineering, University of California, San Diego La Jolla, CA, USA
Department of Electrical and Computer Engineering, University of California, San Diego La Jolla, CA, USA
Department of Electrical and Computer Engineering, University of California, San Diego La Jolla, CA, USA
Contents Department of Electrical and Computer Engineering, University of California, San Diego La Jolla, CA, USA
Department of Electrical and Computer Engineering, University of California, San Diego La Jolla, CA, USA
Department of Electrical and Computer Engineering, University of California, San Diego La Jolla, CA, USA
