Digital phase-locked loops

Digital PLLs exploit CMOS scaling and allow accurate cancellation of fractional spurs and automatic bandwidth control. In Bang-Bang DPLLs assisted by DTC, performance is only li. Digital PLLs exploit CMOS scaling and allow accurate cancellation of fractional spurs and automatic bandwidth control. In Bang-Bang DPLLs assisted by DTC, performance is only limited by DCO and DTC resolution. Bang-Bang DPLLs assisted by DTC allow same phase-noise performance and fractionalspur level as standard DPLLs at much lower power consumption.mited by DCO and DTC resolution. Bang-Bang DPLLs assisted by DTC allow same phase-noise performance and fractionalspur level as standard DPLLs at much lower power consumption.