Loading [a11y]/accessibility-menu.js
Neuromorphic Hardware Architecture Using the Neural Engineering Framework for Pattern Recognition | IEEE Journals & Magazine | IEEE Xplore

Neuromorphic Hardware Architecture Using the Neural Engineering Framework for Pattern Recognition


Abstract:

We present a hardware architecture that uses the neural engineering framework (NEF) to implement large-scale neural networks on field programmable gate arrays (FPGAs) for...Show More

Abstract:

We present a hardware architecture that uses the neural engineering framework (NEF) to implement large-scale neural networks on field programmable gate arrays (FPGAs) for performing massively parallel real-time pattern recognition. NEF is a framework that is capable of synthesising large-scale cognitive systems from subnetworks and we have previously presented an FPGA implementation of the NEF that successfully performs nonlinear mathematical computations. That work was developed based on a compact digital neural core, which consists of 64 neurons that are instantiated by a single physical neuron using a time-multiplexing approach. We have now scaled this approach up to build a pattern recognition system by combining identical neural cores together. As a proof of concept, we have developed a handwritten digit recognition system using the MNIST database and achieved a recognition rate of 96.55%. The system is implemented on a state-of-the-art FPGA and can process 5.12 million digits per second. The architecture and hardware optimisations presented offer high-speed and resource-efficient means for performing high-speed, neuromorphic, and massively parallel pattern recognition and classification tasks.
Published in: IEEE Transactions on Biomedical Circuits and Systems ( Volume: 11, Issue: 3, June 2017)
Page(s): 574 - 584
Date of Publication: 19 May 2017

ISSN Information:

PubMed ID: 28436888

Funding Agency:


References

References is not available for this document.