Memristor panic — A survey of different device models in crossbar architectures | IEEE Conference Publication | IEEE Xplore

Memristor panic — A survey of different device models in crossbar architectures


Abstract:

The popularity of memristors has led to a wide range of models being proposed for both physically realized devices and their concepts in general. These models have been f...Show More

Abstract:

The popularity of memristors has led to a wide range of models being proposed for both physically realized devices and their concepts in general. These models have been fit to specific devices, but the resulting device models are not often discussed in relation to specific applications. A common tool in neuromorphic algorithms, crossbar architectures rely exclusively on the electrical properties of the device connecting rows to columns. Using memristors for these connections, we investigate the viability of 14 device models found in literature for this application. We look at these device models in a crossbar architecture, with supporting circuitry clocked at 500 MHz and providing voltages up to 4V. The two primary functions of a crossbar, evaluating and updating, are both addressed in the context of Rozell et al.'s neuromorphic, Locally Competitive Algorithm (LCA) learning the MNIST dataset and are used to identify the practical qualities of different memristor models. We establish guidelines for designing crossbars regardless of individual device characteristics, and identify a class of devices that produce energy savings when write voltage is relaxed. Our analysis is aimed at assisting researchers with the selection of an appropriate device model, and informing device manufacturers of critical qualities needed from memristive devices for these applications.
Date of Conference: 08-10 July 2015
Date Added to IEEE Xplore: 06 August 2015
Electronic ISBN:978-1-4673-7849-9

ISSN Information:

Conference Location: Boston, MA, USA

I Introduction

In 2008, HP successfully fabricated the fourth circuit element that Chua hypothesized in 1971 [1], [2]. As simple, two terminal devices capable of both storage and computation, memristors may be used for denser networks than their CMOS counterparts. The potential improvements in both computational speed and power efficiency have drawn attention from many research groups, many of whom have proposed their own models of device behavior [3]-[16]. Some of these models are published with parameters fit to physical devices that the researchers have access to, while other models are purely theoretical or extracted from other research groups' published experiment data without any way of validating the model's predictions (details about each model's basis are shown in Table I)

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References

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