Loss-Aware Switch Design and Non-Blocking Detection Algorithm for Intra-Chip Scale Photonic Interconnection Networks

As the number of on-chip processor cores increases, power-efficient solutions are sought for data communication between cores. The Helix-h non-blocking photonic switch is developed to improve physical-layer and network performance parameters for a wide range of silicon nano-photonic multicore interconnection topologies. Traffic benchmarks and practical case studies using a cycle-accurate simulation environment indicate significantly reduced insertion loss providing improved bandwidth density and scalability to manycore plurality. Improvements in system performance parameters are quantified for network bandwidth, transmission efficiency, and latency in popular photonic internconnection topologies, in comparison to previous switch designs. For instance, utilizing the Helix-h switch in a mesh topology, the bandwidth is increased by 112 percent compared to the previously highest performing switch design. Execution time and energy efficiency are improved by up to 92 and 99 percent, respectively, for representative multicore applications. Finally, the technique is generalized to a novel graph-theoretic method for articulating blocking conditions in photonic switches.

1 Introduction

CHIP Multi-Processors (CMPs) have emerged as ubiquitous solution to attaining performance within thermal constraints. Meanwhile, continued increases toward multicore and manycore scalability have led to interconnection challenges due to wiring, energy, and bandwidth limitations. From a performance perspective, interconnection networks are crucial since they connect core elements and also provide off-chip communication. Previous studies have shown that up to half of the dynamic power dissipation can be associated with interconnection in high-performance processors [1]. In addition, as networks scale up, electrical-only means may not be capable of fulfilling communication requirements because of the needed data rate increments and the distance between cores impacting signal drive implications, thus imposing further restrictions on wire densities [2], [3].