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A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation | IEEE Conference Publication | IEEE Xplore

A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation


Abstract:

We present a 500-MHz, ultra-low-power phase-locked loop (PLL) realized with the near-threshold supply voltage of 0.4 V in 65-nm CMOS technology. Our PLL employs a new cha...Show More

Abstract:

We present a 500-MHz, ultra-low-power phase-locked loop (PLL) realized with the near-threshold supply voltage of 0.4 V in 65-nm CMOS technology. Our PLL employs a new charge pump (CP) circuit structure that can greatly reduce CP up/down current mismatch and their variation with voltage-controlled oscillator (VCO) control voltages. The PLL consumes only 127.8 μW, which corresponds to power efficiency of 0.256 mW/GHz.
Date of Conference: 15-17 September 2014
Date Added to IEEE Xplore: 06 November 2014
Electronic ISBN:978-1-4799-3286-3

ISSN Information:

Conference Location: San Jose, CA, USA

References

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