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High Performance BIST PLL approach for VCO testing | IEEE Conference Publication | IEEE Xplore

High Performance BIST PLL approach for VCO testing


Abstract:

RF and mixed signal IC testing is becoming an important issue that affects both the time-to-market and product cost of many modem electronic systems. This paper focuses o...Show More

Abstract:

RF and mixed signal IC testing is becoming an important issue that affects both the time-to-market and product cost of many modem electronic systems. This paper focuses on certain mixed signal IC that is phase locked loop (PLL). A novel BIST (Built-In-Self-Test) approach is developed for RF PLL; it is particularly applied for testing the VCO block. The proposed BIST schema doesn't break the loop to include test circuit in the PLL design stage which is achieved with minimal degradation characteristics of PLL. The key advantage of this technique is that it uses an internal test signal for evaluating the test procedure. The presented architecture uses the existing elements for measuring and testing in order to reduce the area overhead for BIST schema, solves the analog nodes loading problem and improves the test accessibility. The test output generated is a purely digital signal. The BIST method enables the detection of catastrophic and many parametric faults affected the VCO by measuring its oscillation frequency response. To evaluate the effectiveness of proposed BIST approach, a fault simulation results indicate the characteristic of the BIST structure that is high fault coverage of 100%.
Date of Conference: 17-19 March 2014
Date Added to IEEE Xplore: 16 June 2014
Electronic ISBN:978-1-4799-4888-8
Conference Location: Sousse, Tunisia

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