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UML state machine implementation in FPGA devices by means of dual model and Verilog | IEEE Conference Publication | IEEE Xplore

UML state machine implementation in FPGA devices by means of dual model and Verilog


Abstract:

The paper presents the methodology of the logic controller development process based on the UML state machine diagram. The development process covers the logic synthesis ...Show More

Abstract:

The paper presents the methodology of the logic controller development process based on the UML state machine diagram. The development process covers the logic synthesis and the implementation by means of the intermediate model based on Petri net formalism. The transformation between these two formal models is performed at the metamodels level according to the Model Driven Architecture (MDA). Semantics of the hierarchical configurable Petri net (HCfgPN) was adopted for the preemption and resumption mechanism. Operational subnet of HCfgPN model may be verified using formal methods.
Date of Conference: 29-31 July 2013
Date Added to IEEE Xplore: 10 October 2013
Electronic ISBN:978-1-4799-0752-6

ISSN Information:

Conference Location: Bochum, Germany

References

References is not available for this document.