A 100-GHz balanced FET frequency doubler in 65-nm CMOS | IEEE Conference Publication | IEEE Xplore

A 100-GHz balanced FET frequency doubler in 65-nm CMOS


Abstract:

This paper demonstrates a W-band CMOS frequency doubler which utilizes a balanced topology in order to achieve a wideband fundamental suppression. The required 180-degree...Show More

Abstract:

This paper demonstrates a W-band CMOS frequency doubler which utilizes a balanced topology in order to achieve a wideband fundamental suppression. The required 180-degree phase shift is obtained by employing a spiral transmission line balun. At 100 GHz the measured conversion loss of the frequency doubler is 16 dB using an input power of +5 dBm. The fundamental suppression is better than 25 dB from 42 to 55 GHz.
Date of Conference: 10-11 October 2011
Date Added to IEEE Xplore: 15 December 2011
ISBN Information:
Conference Location: Manchester, UK

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