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Efficient Reconfigurable On-Chip Buses for FPGAs | IEEE Conference Publication | IEEE Xplore

Efficient Reconfigurable On-Chip Buses for FPGAs


Abstract:

This paper presents techniques for generating on-chip buses suitable for dynamically integrating hardware modules into an FPGA-based SoC by partial reconfiguration. The b...Show More

Abstract:

This paper presents techniques for generating on-chip buses suitable for dynamically integrating hardware modules into an FPGA-based SoC by partial reconfiguration. The buses permit direct connections of master and slave modules to the bus in combination with a flexible fine-grained module placement and with minimized latency and area overheads. A test system will demonstrate a transfer rate of 800 MB/s while providing an extreme high placement flexibility.
Date of Conference: 14-15 April 2008
Date Added to IEEE Xplore: 22 December 2008
Print ISBN:978-0-7695-3307-0
Conference Location: Stanford, CA, USA

References

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