Abstract:
Intrinsic and parasitic capacitances play an important role in determining the high-frequency RF performance of devices. Recently, a new type of carbon nanotube field eff...Show MoreMetadata
Abstract:
Intrinsic and parasitic capacitances play an important role in determining the high-frequency RF performance of devices. Recently, a new type of carbon nanotube field effect transistor (CNFET) based on tunneling principle has been proposed, which shows impressive device properties and overcomes some of the limitations of previously proposed CNFET devices. Although carbon nanotube based devices have been optimized for DC performance so far, little has been done to optimize them for high-frequency operation. In this paper, we present, detailed modeling and analysis of device geometry based intrinsic and parasitic capacitances of tunneling carbon nanotube field effect transistors (T-CNFETs) with both single nanotube as well as nanotube-array based channel. Based on the model, we analyze scaling of parasitic capacitances with device geometry for two different scaling scenarios of T-CNFETs. We show that in order to reduce the impact of parasitic capacitance, nanotube density has to be optimized. Furthermore, for the first time, we analyze various factors affecting the high-frequency/RF performance of back gated T-CNFETs and study the impact of parasitic and screening effects on the high-frequency/RF performance of these devices.
Published in: 2008 45th ACM/IEEE Design Automation Conference
Date of Conference: 08-13 June 2008
Date Added to IEEE Xplore: 02 July 2008
Print ISBN:978-1-60558-115-6
Print ISSN: 0738-100X