A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction | IEEE Journals & Magazine | IEEE Xplore

A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction


Abstract:

A low phase noise, delay-locked loop-based programmable frequency multiplier, with the multiplication ratio from 13 to 20 and output frequency range from 900 MHz to 2.9 G...Show More

Abstract:

A low phase noise, delay-locked loop-based programmable frequency multiplier, with the multiplication ratio from 13 to 20 and output frequency range from 900 MHz to 2.9 GHz, is reported in this brief. A new switching control scheme is employed in the circuit to enable the capability of locking to frequencies either above or below the start-up frequency without initialization. To reduce the spurious output power level, a low-bandwidth auxiliary loop [period error compensation loop (PECL)] is employed to compensate for the output period error caused by the phase realignment errors. This frequency multiplier is implemented in TSMC 0.18-mum CMOS technology and measured with a synthesized frequency source. A significant reduction of the output spurs from -23 to -46.5 dB at 1.216 GHz is achieved by enabling the PECL. The measured cycle-to-cycle timing jitter at 2.16 GHz is 1.6 ps (rms) and 12.9 ps (pk-pk), and the phase noise is -110 dBc/Hz at 100-kHz offset with a power consumption of 19.8 mW at a 1.8-V power supply
Published in: IEEE Transactions on Circuits and Systems II: Express Briefs ( Volume: 53, Issue: 11, November 2006)
Page(s): 1205 - 1209
Date of Publication: 13 November 2006

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