Abstract:
In this paper, the application of a four-valued logic to the switch-level test generation is studied. A switch-level operator fault model is proposed. Switch-level U diff...Show MoreMetadata
Abstract:
In this paper, the application of a four-valued logic to the switch-level test generation is studied. A switch-level operator fault model is proposed. Switch-level U difference and Z difference of a function to a fault are defined. A method to derive switch-level differences is given. Finally, a new switch-level test generation algorithm for CMOS circuits is presented.<>
Date of Conference: 25-27 May 1994
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-8186-5650-6