Abstract:
A novel Pillar phase change memory based on fully integrated test arrays in 180nm CMOS technology has been successfully fabricated. A current-confining Pillar structure l...Show MoreMetadata
Abstract:
A novel Pillar phase change memory based on fully integrated test arrays in 180nm CMOS technology has been successfully fabricated. A current-confining Pillar structure leads to a self-heating at the center of the chalcogenide layer, and needs only one additional mask level for its fabrication. Switching characteristics with write currents less than 900μA at 75nm diameter and multilevel operation are reported
Date of Conference: 13-15 June 2006
Date Added to IEEE Xplore: 02 October 2006
Print ISBN:1-4244-0005-8