Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors

To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constraints, distributed register files, variable-length encodings for instructions, and special data paths are frequently adopted. This creates challenges to deploy software toolkits for new embedded DSP processors. This article presents our methods and experiences to develop software and toolkit flows for PAC (parallel architecture core) VLIW DSP processors. Our toolkits include compilers, assemblers, debugger and DSP micro-kernels. We first retarget open research compiler (ORC) and toolkit chains for PAC VLIW DSP processor and address the issues to support distributed register files and ping-pong data paths for embedded VLIW DSP processors. Second, the linker and assembler are able to support variable length encoding schemes for DSP instructions. In addition, the debugger and DSP micro-kernel were designed to handle dual-core environments. The footprint of micro-kernel is also around 10K to address the code-size issues for embedded devices. We also present the experimental result in the compiler framework by incorporating software pipeline (SWP) policies for distributed register files in PAC architecture. Results indicated that our compiler framework gains performance improvement around 2.5 times against the code generated without our proposed optimizations

1. Introduction

With the fast growth of consumer electronic products, the demand on digital signal processings related to the multimedia, such as image and video processing, is also increased significantly. To meet the performance challenges, high-end embedded processor and DSP processors are moving towards exploiting intensively instruction level parallelism (ILP). In addition, the tight resources in embedded systems also have DSP processors to adopt architecture features such as distributed register files to reduce the amount of read and write ports in registers to reduce power consumptions [1], special data path to exploit the characteristics of DSP applications, variable length encoding schemes for instructions to reduce code size, the sub-word instructions for video applications, etc. The appearance of these new features create challenges to deploy software toolkits for new embedded DSP processors.