Abstract:
65 nm node SoC technology has been achieved to show good yield of 8 Mbit DRAM ADM using tapered BF/sub 2/ implantation without an additional mask step, the cell size of w...Show MoreMetadata
Abstract:
65 nm node SoC technology has been achieved to show good yield of 8 Mbit DRAM ADM using tapered BF/sub 2/ implantation without an additional mask step, the cell size of which is 0.11 /spl mu/m/sup 2/, with 3 layers of hybrid low-k material, SiLK/BD/BLOk, and Cu integration.
Published in: IEEE International Electron Devices Meeting 2003
Date of Conference: 08-10 December 2003
Date Added to IEEE Xplore: 03 March 2004
Print ISBN:0-7803-7872-5
Contents 