A New Distributed Attenuator Using DTMOS-With-RB-and Diode-Connected-FET-Based Varistor Units

A passive distributed attenuator with high linearity and a wide attenuation range is presented. It consists of four parallel varistor units and three sections of series λ/8-transmission line (TL)-based λ/6 and 50-Ω synthetic TLs. Each varistor unit consists of a cascode of DTMOS-with-R_B FETs (DFET) M₁/M₂ in parallel with a cascode of DFET M₃ and diode-connected FET M₄ and then in series with TL₂ for phase compensation of parasitic capacitance. In the low-attenuation state (V_ct = 0 V), input 1-dB compression point (IP_1dB) boosting is attained due to the cascode of M₁/M₂ and the slowdown of M₁ turn-on by the leakage suppression of R_B. In the high-attenuation state (V_ct = 2 V), low gain expansion (smaller than 1 dB for P_in up to 20 dBm) is achieved since the varistor unit is equivalent to a parallel resistance (R) of 70 Ω for V_in of -4 to 4 V. This is attributed to the cascode of M₃/M₄ providing a second conduction path at V_in that is larger than V_ct - V_th (1.7 V), where M₂ enters the high R saturation region from the low R linear region. The attenuator achieves IP_1dB,att (P_in at 1-dB attenuation range reduction) of 20 dBm, one of the best IP_1dB,att results ever reported for (Bi)CMOS attenuators. For 4-bit attenuation control (-4 to -19 dB) with 1 dB/step, the attenuator achieves an rms gain error of 0.01–0.5 dB and an rms phase error of 4.5^∘–5.9^∘ for 37–41 GHz.