TID-Tolerant StrongARM Comparator and Sampling Network for Satellite Application High-Voltage ADCs

Semiconductor devices for satellite applications must be robust in irradiation environments, up to 100 krad of total ionizing dose (TID) over a 10-year space mission [1]. While low-voltage (LV) processes exhibit higher TID resilience owing to their thin gate oxide (Gox) (<10 nm) [2], highvoltage (HV) circuits such as ADCs required for various monitoring purposes in satellites still require solutions to the TID-induced threshold $\left(\mathrm{V}_{\mathrm{TH}}\right)$ shift problem: trapped holes by TID in NMOS gate oxide decrease $\mathrm{V}_{\mathrm{TH}}$ (whereas $\left|\mathrm{V}_{\mathrm{TH}}\right|$ in PMOS increases). Fig. 1 illustrates this phenomenon along with the equivalent circuit model. $\mathrm{V}_{\mathrm{TH}}$ shift $\left(\Delta \mathrm{V}_{\mathrm{TH}, \mathrm{TID}}\right)$ is modeled with a voltage source on the gate and the additional leakage path through the field oxide (Fox) is modeled with a lumped NMOS, Mn,Fox. From our TID test, $\Delta \mathrm{V}_{\mathrm{TH}, \mathrm{TID}}$ of an NMOS in our $0.35 \mu \mathrm{~m} \mathrm{HV}$ CMOS technology is measured to be 1.5 V and 2.5 V at the TID levels of 50 krad (TID-1) and 100 krad (TID-2), respectively. To consider even worse case scenarios, $\Delta \mathrm{V}_{\mathrm{TH}, \mathrm{TID}}$ is extrapolated as 3 V (TID-3) and 4 V (TID-4). It is worth to note that our HV NMOS switches cannot be turned off even at TID-1 level because its typical $\mathrm{V}_{T H}$ is 1.48 V, while $\left|\mathrm{V}_{\mathrm{TH}}\right|$ increase in PMOS benignly reduces their on conductance (gon).